Re: [SI-LIST] : RE: [SI-LIST]: Long bus or star?

D. C. Sessions (dc.sessions@vlsi.com)
Mon, 29 Mar 1999 16:00:09 -0700

Chris Bobek wrote:
>
> >How do you propose to keep several legs ALL less than 12mm long?
> >(at least 60ps/cm, risetime of less than 300ps, line length
> >Tr/4 => 1.25cm) Note that this is a foolishly optimistic
> >calculation.
>
> Where did you get 300ps for the risetime? I was using 3ns.

Assuming that you can still find something that slow, or can
have one custom-designed (not cheap -- I know whereof I speak
since custom I/O design is what I do here....)

Lacking a supply of 74LS devices or a budget for full-custom
silicon, you're pretty much stuck with the native edge rates
for standard silicon. Assuming that your product is behind
the curve but not too far (say 350-500nm technology, the
stuff that likes 3.3v) then you can figure on worst-case (slow)
edge rates in the 300-600ps range and fast-case ones about
60% of that.

IOW, 300ps or faster.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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