Re: [SI-LIST] : 20-H Rule for Power Planes

Chris Padilla (cpad@cisco.com)
Thu, 27 May 1999 16:19:48 -0700

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Good points, Mike.

We have just recently been able to do a similar study here at Cisco.
We had 48-port 10BaseT board that was spun in two flavors: one
with most metal removed in the I/O area and one with most metal
left in at the I/O area. This metal was for all intents and
purposes tied to a zero-potential reference . So, other than the
metal quantities in the front-end, the boards were identical.

The results? The one with most metal left in the front end and tied
to zero-potential metal had better results in the anechoic chamber
by a rough average of 4-5 dB for this board's particular clocks and
associated harmonics.

It is not exactly what you were describing but I think the general
idea is there for getting the noodle working.

Thanks

>I have no experience one way or the other with this, but I get
>suspicious of rules that have no solid data to back them up. A similar
>EMC type issue that affects alot of boards is whether to create an
>isolated chassis ground at I/O connectors or connect the logic ground
>directly to chassis ground. Some references say do it, some say
>don't. The only study I have seen was done by or with Sun and tried to
>compare two boards that only differed in the way the ground plane was
>handled at the I/O interface. As I recall, connecting the plane to
>chassis ground was much better than having an isolated I/O ground.
>
>The people advocating the isolated ground approach may never have
>looked closely and really compared to boards that differed *only* in
>the connection. THerefore they are really just saying "it has always
>worked for me".
>
>I would be very interested in simulation results.
>
>--
>=============================================================================
>Mike Mayer Artesyn Communication Products, Inc
> Madison, WI
> http://www.artesyn.com/cp
>=============================================================================

Chris Padilla C i s c o S y s t e m s
EMC Engineer __________________________
170 West Tasman Drive | |
San Jose, CA 95431 | |
Email: cpad@cisco.com | | | |
Work: 408.525.4989 | !|! !|! |
Pager: 408.870.5410 | .!|||!. .!|||!. |
Fax: 408.525.9150 |.:!!!!!!!!!:..:!!!!!!!!!:.|

"I think the best evidence that intelligent life exists
elsewhere in the universe is that none of it has tried
to contact us...." Calvin of Calvin & Hobbes
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Good points, Mike.

We have just recently been able to do a similar study here at Cisco.
We had 48-port 10BaseT board that was spun in two flavors:  one
with most metal removed in the I/O area and one with most metal
left in at the I/O area.  This metal was for all intents and
purposes tied to a zero-potential reference .  So, other than the
metal quantities in the front-end, the boards were identical.

The results?  The one with most metal left in the front end and tied
to zero-potential metal had better results in the anechoic chamber
by a rough average of 4-5 dB for this board's particular clocks and
associated harmonics.

It is not exactly what you were describing but I think the general
idea is there for getting the noodle working.

Thanks

>I have no experience one way or the other with this, but I get
>suspicious of rules that have no solid data to back them up. A similar
>EMC type issue that affects alot of boards is whether to create an
>isolated chassis ground at I/O connectors or connect the logic ground
>directly to chassis ground. Some references say do it, some say
>don't. The only study I have seen was done by or with Sun and tried to
>compare two boards that only differed in the way the ground plane was
>handled at the I/O interface. As I recall, connecting the plane to
>chassis ground was much better than having an isolated I/O ground.
>
>The people advocating the isolated ground approach may never have
>looked closely and really compared to boards that differed *only* in
>the connection. THerefore they are really just saying "it has always
>worked for me".
>
>I would be very interested in simulation results.
>
>--
>=============================================================================
>Mike Mayer                               Artesyn Communication Products, Inc
>                                         Madison, WI
>                                         http://www.artesyn.com/cp
>=============================================================================

Chris Padilla            C i s c o  S y s t e m s
EMC Engineer            __________________________
170 West Tasman Drive  |                          |
San Jose, CA  95431    |                          |
Email: cpad@cisco.com  |      |            |      |
Work:  408.525.4989    |     !|!          !|!     |
Pager: 408.870.5410    |   .!|||!.      .!|||!.   |
Fax:   408.525.9150    |.:!!!!!!!!!:..:!!!!!!!!!:.|

"I think the best evidence that intelligent life exists
elsewhere in the universe  is that none of it has tried
to contact us...."  Calvin of Calvin & Hobbes

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