FW: [SI-LIST] : Chip level Vs Board level SI

Shenoy, Jay (Jay.Shenoy@VLSI.com)
Thu, 15 Apr 1999 12:14:13 -0700

Just a sampler of chip level SI problems:

* Crosstalk, both for noise and cross-talk induced delay (a capacitive
analogue of SSO )
* Power-Ground resonance: heavily damped, but lots of localized capacitance
( the cause of the heavy damping, i.e. IR-drop, is also usually considered
SI and is a big problem)
* Distribution of long signals (esp clocks) sees the R*L*C effects , L kicks
in when the
edge rates are fast and your power/ground return path design not good
enough. Even without
L, people have long been doing RC transmission line analysis (even if they
dont know it)
* Driving multidrop buses, same as above except even more capacitive than
board level
* Especially in silicon - ground wave effect, with poor return paths in
metal, since this then
a lossy dielectric for the return, which is nonhomogenous to boot! (the
Si/SiO2 stack that is).

Almost a 1:1 correspondence with some major board level problems.

Poor return paths is a recurring theme, IMHO the biggest SI "problem" on
chip is that quite
a few transistor level designers are extremely tuned to thinking of a signal
being propogated on
*one* wire only. Otherwise, the simplest rules of thumb on return paths,
would all but alleviate
many of the on-chip SI problems that can really bite.

On-soapbox: Not to mention that most physical design is done by automated
P&R tools
and so, even whom to hammer the above points into, is completely unclear!
Off-soapbox.

Regards
Jay

> -----Original Message-----
> From: Arun Chandrashekar [SMTP:carun@cedt.iisc.ernet.in]
> Sent: Thursday, April 15, 1999 11:11 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Chip level Vs Board level SI
>
> Hello all,
> I need some information on factors that distinguish signal
> integrity problems at the chip level and at the board level. I
> personally feel that board level SI problems are more prominent as I do
> not have much idea about the chip level SI problems. Also, most articles
> I come across do not seem to address the SI problems at the chip level.
> Can u help me throw light on this point and clarify ?
> Thanks and Regards
> ARUN C
> Research Associate
> CEDT, Indian Institute of Science
> Bangalore, Karnataka, INDIA
> 560012
> Ph: +91-80-3341810
> FAX: +91-80-3341808
> Homepage URL: http://shravana.cedt.iisc.ernet.in/~carun
>
>
>
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