[mailto:email@example.com]On Behalf Of HaroldLSJ@aol.com
Sent: Sunday, October 10, 1999 2:26 AM
To: firstname.lastname@example.org; Alex.Theodorou@abq.sc.philips.com
Subject: Re: [SI-LIST] : Clock Skew Measurements
If you need to measure 35 picoseconds or less of skew then contact
They have a tester that will directly measure your problem. Check
www.wavecrest.com for further details and info. I have used their equipment
and it is very accuarate.
Scientist & Consultant
Begin Included Message:
> Subj: [SI-LIST] : Clock Skew Measurements
> Date: 10/8/1999 6:39:19 PM Central Daylight Time
> From: Alex.Theodorou@abq.sc.philips.com (alext)
> Sender: email@example.com
> Reply-to: firstname.lastname@example.org
> To: email@example.com
> Hi SI Gurus,
> Anybody out there have any ideas on how to do production
> testing of clock output skew (output pin to output pin)
> on a clock distribution chip?
> I've got 2 different chips.
> The first chip has 1 PECL input and 10 PECL outputs.
> The maximum input frequency is 1.5 GHz, and the
> maximum clock output skew is spec'd at 35ps.
> The second chip is a lot like the first except that it's
> got an LVDS input and LVDS outputs. The specs on this one
> are 800 MHZ max input frequency and the maximum clock output
> skew is spec'd at 35ps.
> I'm somewhat constrained by the capabilities of my tester
> (Credence Vista Logic). Maybe I need to use some indirect
> technique with active circuitry on the load-board?.
> Thanks in advance for your suggestions.
> Alex Theodorou
End Included Message.
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