Mike
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of [email protected]
Sent: Sunday, October 10, 1999 2:26 AM
To: [email protected]; [email protected]
Subject: Re: [SI-LIST] : Clock Skew Measurements
Alex,
If you need to measure 35 picoseconds or less of skew then contact
Wavecrest.
They have a tester that will directly measure your problem. Check
www.wavecrest.com for further details and info. I have used their equipment
and it is very accuarate.
Harold Snyder
Scientist & Consultant
Begin Included Message:
============================
> Subj: [SI-LIST] : Clock Skew Measurements
> Date: 10/8/1999 6:39:19 PM Central Daylight Time
> From: [email protected] (alext)
> Sender: [email protected]
> Reply-to: [email protected]
> To: [email protected]
>
> Hi SI Gurus,
>
> Anybody out there have any ideas on how to do production
> testing of clock output skew (output pin to output pin)
> on a clock distribution chip?
>
> I've got 2 different chips.
>
> The first chip has 1 PECL input and 10 PECL outputs.
> The maximum input frequency is 1.5 GHz, and the
> maximum clock output skew is spec'd at 35ps.
>
> The second chip is a lot like the first except that it's
> got an LVDS input and LVDS outputs. The specs on this one
> are 800 MHZ max input frequency and the maximum clock output
> skew is spec'd at 35ps.
>
> I'm somewhat constrained by the capabilities of my tester
> (Credence Vista Logic). Maybe I need to use some indirect
> technique with active circuitry on the load-board?.
>
> Thanks in advance for your suggestions.
>
> Regards,
>
> Alex Theodorou
============================
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