Ah! I agree that providing I/O bypass capacitance on-chip is hideously
expensive, due in equal part to the huge amount of charge storage needed
and to the limited benefit it provides (essentially it allows the use of
both supply and ground wires to supply SSO transients instead of just one
or the other.)
IMHO the best bet for minimizing SSO transients is to use balanced codes
such as 8b/10b so that there isn't any substantial common-mode current.
Actually saves pins and cuts jitter too.
> -----Original Message-----
> From: D. C. Sessions [mailto:email@example.com]
> Sent: Monday, September 20, 1999 9:08 AM
> To: firstname.lastname@example.org
> Subject: Re: [SI-LIST] : RE: Another decoupling question
> "Volk, Andrew M" wrote:
> > Chris -
> > I agree the best capacitance is on-die. It is expensive in die area, but
> > becoming more and more essential as edge rates and speeds increase.
> > However, there exist devices already without such provisions and I was
> > wondering whether capacitors can be placed under BGA packages to help
> > existing power decoupling problems. Is it cost effective and
> > manufacturable?
> > -----Original Message-----
> > From: Chris Cheng [mailto:email@example.com]
> > Sent: Friday, September 17, 1999 1:52 PM
> > To: firstname.lastname@example.org
> > Subject: RE: [SI-LIST] : RE: Another decoupling question
> > for ~10nf, you are better of putting it insider the die. (yes, on
> > die decouping)
> > chris
-- D. C. Sessions email@example.com
**** To unsubscribe from si-list: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****