Re: [SI-LIST] : A Question About Power Noise.

fabrizio zanella ([email protected])
Fri, 19 Mar 99 9:30:50 -0500

Larry, thanks for the great information about your past experiences with
decoupling! Can you share with us how you calculate the loop inductance
from the power planes through traces and vias to chips? This seems as it
would be a difficult calculation.
Also, is the material you presented at last year's Electrical Performance
of Electronic Packaging (EPEP) conference available somewhere? It seems
like very worthwhile reading to understand an important issue. For those of
you who did not attend DesignCon, power noise seems to be the next big
hurdle for signal integrity engineers to solve.

Fabrizio Zanella
EMC, Hardware Engineering
[email protected]
508-435-2075, x4645
Original Text
From: "Larry Smith" <[email protected]>, on 3/18/99 2:17 PM:
To: [email protected]@EMCHOP1[<[email protected]>]

The question is: "Is it better to connect decoupling capacitors
directly to the power planes with vias, or to connect a chip to the
capacitor with traces and then via to the power planes on the far side
of the capacitor?" Doug Brooks wants answers.

Been there, done that.. several years ago.. It's a little late, but I
will report the results now.

As several posters have already pointed out, the answer may be
different for analog and digital applications, and may depend on your
reasons for decoupling. Placement of the capacitor between the chip
and the power planes will protect the power planes from high frequency
noise. It is a T filter involving the capacitor and inductors (traces
or vias) to the left and right of the capacitor. But, the filter works
both ways. If the power planes are considered to be an ideal voltage
source, the chip will look out through the filter and see a high
impedance at one or more frequencies caused the parallel resonance of
the capacitor and the far inductance. If the chip tries to draw power
at that frequency... curtains. The failure can come in the form of a
chip that does not work or high EMI emissions at that resonant

I have come to the conclusion that it is much better to attach
decoupling capacitors directly to tightly coupled (closely spaced)
power planes. Then connect the chip in the same way. The systems I
deal with tend to have dozens if not 100's of pairs of Vdd/Gnd
connections from the ASIC or uP to the power planes. A very low (10's
of pH) loop inductance from the chip to PCB power planes is established
in this way. The planes are then decoupled with dozens of high
frequency capacitors on low inductance pads. As discussed yesterday,
the inductance in the capacitor/power-plane loop is under 1nH. By this
method, we have established a sufficiently low impedance path to
conduct charge from the capacitors to the chip, when the chip demands
transient current. Transient demands can easily be 10 amps in 10 nSec
= 1amp/nSec = di/dt. V=L di/dt and if we want to have much less than 1
volt of noise on our power supply, the inductance had better be much
less than 1 nH.

Let's look at the numbers for the alternative approach. A pair of 12
mil wide surface traces that are spaced 6 mils apart have a loop
inductance that is 9.33 nH/inch (by my extractor). So, if the pair of
traces are more than 50 mils long, we have exceeded the partial
inductance due to the capacitor pads and vias used to hook a capacitor
to power planes. It will be very difficult to place capacitors within
50 mils of the power pins on an ASIC.

But I tried to do it one time... I had about a dozen Vdd/Gnd pairs on
the inside rows of a CBGA. I used vias near the Vdd/Gnd solder bumps
to get to the back side of the PCB. I used very wide traces to pass
underneath two sets of decoupling capacitor pads, thinking that I was
going to make a very nice filter. Finite element analysis (after the
artwork was released, of course) showed that the loop inductance from
the power planes through the traces and vias to the chip solderballs
was over 9 nH..! The system actually worked, but I breathed a sigh of
relief when the project was canceled. The power planes were nice and
clean noise wise, but there were certain frequencies where the chip was
not allowed to draw current, and customer code is kind of hard to
predict. Spice simulation of the structure showed some pretty ugly
power waveforms at the chip. ...Well, I'll never do that again.

Doug - we appreciate fine work your company has done and the published
material in Printed Circuit Design magazine. I believe the whole
industry benefits from open discussion like this. We have published
a portion of our work at last year's EPEP conference in the form
of a paper and class on power distribution. If things go well, we
will have a full length paper in the CPMT journal next August that
deals more with the decoupling and power distribution topic.

Larry Smith
Sun Microsystems

> X-Sender: [email protected]
> Date: Wed, 17 Mar 1999 16:53:41 -0800
> To: [email protected], [email protected]
> From: Doug Brooks <[email protected]>
> Subject: Re: [SI-LIST] : A Question About Power Noise.
> Mime-Version: 1.0
> Perhaps you can hear my chuckling in the background, here.
> Once apon a time, I advocated running traces from caps to devices. My
> reason, primarily, was to keep noise off the planes. I took quite a bit
> heat from many people who said that routing to the plane was a MUCH lower
> inductance way to route.
> Now you provide information that (might) suggest that even if the plane
> NO inductance, there is inductance in the vias getting back and forth
> the planes to the caps and devices. So the planes, in the total picture
> might not be the lowest inductance way to route afterall. And,
> interestingly enough, Michael Zhang then says the HP (Printer Division)
> routes using traces to keep noise off the plane (If I understood his
> properly).
> Then the argument shifts from inductance to loop area (a view that, at
> least I, hadn't heard before). This, in fact, might be a pretty good
> argument. Even if the loops on the planes are of similar length, there is
> at least some shielding there that does not exist around surface traces.
> So here is my challenge to some of you. My company has tried to design,
> test, and report on two areas in the past --- the effects of vias on
> and the effects of 90 degree corners on PCB's. The results of both
> investigations appeared in PCB Design and copies are available on our web
> site. My company does not have the resources to conduct an experiment on
> bypass caps (although we will certainly participate to the extent we can
> help). Some of you DO have the resources. So lets have a few people
> associated with this group figure out how to design and control an
> experiment that will resolve these issues once and for all, and share
> results with the rest of the community.
> I hope someone picks up the challenge.
> Doug Brooks
> .
> ****************************************************
> Doug Brooks, President [email protected]
> UltraCAD Design, Inc.
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