# Re: [SI-LIST] : Via Capacitances ...

Fred Balistreri (*fred@apsimtech.com*)

*Fri, 09 Jul 1999 14:10:23 -0700*

Dr. Edward P. Sayre wrote:

*> *

*> Folks:*

*> *

*> It may not be convenient and may stress your personnel or financial*

*> assests, but this is why you make SI measurements to confirm your results.*

*> Almost anybody who has made the measurement knows that vias for whatever*

*> reason turn out to be capacitive. If one checks with Dr. Johnson's book,*

*> you will find that vias are modeled by both capacitors and inductorance.*

*> By both measurement and SPICE simulation, NESA has shown this to be true.*

*> (See papers on our web site.)*

*> *

*> (The next sentence should be read in the context that I was one of the*

*> original students involved in the development of the Method of Moments*

*> field simulators and know a lot about old and new simulation software.)*

*> There is ample evidence to show that many field simulator derived SPICE*

*> models (especially those from 2-D simulators) are often unreliable with*

*> respect to the component values but usually have the correct topology.*

*> That is to say, if you make a measurement and then adjust the SPICE*

*> component values and re-simulating one or twice, you can get satisfactory*

*> comparisons with the measurements.*

*> *

*> Otherwise, there is no way to verify the correctness of field solver*

*> derived SPICE models for interconnect physical features like vias or*

*> connectors.*

*> *

*> ed sayre*

*> ============*

*> At 09:50 AM 7/9/99 -0700, you wrote:*

*> >Doug*

*> >*

*> >I modeled a via some time back with ground planes and*

*> >clearance holes through it. I had intended to use the capacitance*

*> >to make up for an inductance and needed 300 ff.*

*> >*

*> >I used an OEA field solver Metal and to my amazement there was*

*> >hardly any capacitance. I surmised that this was due to the small*

*> >area of the ground planes in tha horizontal direction. Since I needed*

*> >capacitance I added some big fat ground vias all around the signal*

*> >via, and got the 300 ff.*

*> >*

*> >Also, HP ADS which is the cadillac of RF simulators models vias*

*> >as inductor, as does Touchstone before EEsof got swallowed up by*

*> >HP.*

*> >*

*> >Ron*

*> >*

*> >Douglas McKean wrote:*

*> >*

*> >> Could someone give rough estimate*

*> >> of via capacitance?*

*> >>*

*> >> I'm thinking the orientation of the traces*

*> >> connected to the via have a major impact.*

*> >>*

*> >> For instance, an .062 board with a via*

*> >> from one side to the other, different*

*> >> capacitances would be had with the two*

*> >> following constructions ...*

*> >>*

*> >> I. Top Trace*

*> >> -------------*

*> >> |via*

*> >> -------------*

*> >> Bottom Trace*

*> >>*

*> >> II. Top Trace*

*> >> -------------*

*> >> |via*

*> >> -------------*

*> >> Bottom Trace*

*> >>*

*> >> Ideas? Comments?*

*> >>*

*> >> Regards, Doug McKean*

*> >>*

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*> >*

*> >--*

*> >Ronald B. Miller _\\|//_ Signal Integrity Engineer*

*> >(408)487-8017 (' 0-0 ') fax(408)487-8017*

*> > ==========0000-(_)0000===========*

*> >Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131*

*> >rmiller@brocade.com, rbmiller@sjm.infi.net*

*> >*

*> >*

*> >*

*> >*

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*> >*

*> *

*> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+*

*> | NORTH EAST SYSTEMS ASSOCIATES, INC. |*

*> | ------------------------------------- |*

*> | "High Performance Engineering & Design" |*

*> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+*

*> | Dr. Ed Sayre e-mail: esayre@nesa.com |*

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I'm not sure what people mean when they say its capacitive or inductive.

A via consist of capacitance, inductance and resistance. It is true

that for normal PCB designs a via would have a lower impedance profile

than a 50-80 ohm PCB trace when subjected to a TDR pulse. Because of

the sqrt l/c equation one may conclude that the ratio of capacitance

to inductance is higher on a via than a trace. This may be true in

most designs but is by no means a rule. The physical dimension of the

via and the proximity to gnd/pwr planes will determine this ratio.

As mentioned previously, the size of the cutout in the planes when the

via passes through them also has a large impact on capacitance. There

are 2d solvers that do a respectable job of calculating a via model.

We currently are seeing some designs with microvias. Those type of vias

tend to have a ratio that may lend them to be "inductive" when compared

to PCB traces. So I can't believe any of the arguments I've heard so

far. A measurement is only good for the structure you are measuring.

If the structure changes one cannot apply the same rules without first

obtaining more data points. Its always a good sanity check to see if

the measurement results tend to agree with theory as well. High

frequency measurements of this type are not the easiest to make.

Best Regards,

--
Fred Balistreri
fred@apsimtech.com
http://www.apsimtech.com

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