> [email protected] wrote:
>
> > I have seen warnings about "buried capacitance" layers that use high-Er
> > materials. While this is OK at lower frequencies, the advantage falls apart
> > at higher frequencies because the propagation delay through the buried
> > capacitance layer is more. Even though the capacitance per unit area is
> > large, the capacitance per nanosecond (risetime) may not be.
> >
> > Andy
>
> A good point! The main argument usually made regarding the use of of
> high Er dielectric materials is that they enable the inclusion of very
> high amounts of capacitance/area in a PCB. While this is true, there
> is more to be considered.
>
> While a high Er constant enables a higher capacitance, it also has another
> effect: that of slowing down the time of flight of signal associated with
> the high Er dielectric layer.
>
> Consider the scenario where a planar stackup is modified only by
> changing the Er of the substrate material from say 4.0 to 40 .
> Let's analyze what happens:
>
> First the capacitance per unit area within the layer increases by the
> ratio of the dielectric constants since:
>
> Eo*Er*A
> C = -------
> D
>
> (changing Er from 4 to 40 causes capacitance/unit area to increase 10X)
>
>
> Second, the time of flight increases by the square root of the ratio of
> the dielectric constants since:
>
> Dist
> Tf = ---------
> C/sqrt(Er)
>
> (changing Er from 4 to 40 causes Tof to increase 3.16 times)
>
>
> Since the time of flight has increased, it takes longer for charge stored in
> the dielectric to reach a "point of consumption" or sink point on the plane.
> So if a circuit needs current in say 1ns and charge is traveling 1/3.16
> slower then the radius of the "effective capacitance" is 1/3.16 the size
> of the original radius.
>
> We know that the area of a circle is: A= (pi * r^2) . So if the radius
> is 1/3.16 the original then the area is 1/10 the original area.
>
> Since the capacitance / unit area increased 10 X then the
> "available capacitance" is 1/10 * 10 = 1 X the original !
Does this mean ,for a given PCB size, I can increase the number of "points of consumption"
by a factor of 10 and maintain the same capacitance per "point of consumption"?
>
>
> Therefore even though the capacitance per unit area has increased
> 10X, the available capacitance to supply current within a specified
> time hasn't increased a bit. At lower frequencies the slowing of the
> time of flight isn't an issue, but then again we usually aren't depending
> on the charge storage capailities of the planes at those frequencies anyway.
Will this lower the resonant frequency of the PCB power planes?
>
>
>
> Decreasing the separation between the planes WILL improve matters. Making
> the interplanar spacing 1/10 of the original spacing increases the
> capacitance by a factor of 10 and doesn't affect the speed of propagation.
> In addition, the close plane spacing reduces the planar spreading inductance
> giving you a big gain there too
Typically interplane spacing is 5 or 10 mil.
Reducing this by 1/10 is not a real option.
>
>
>
> Ray Anderson
> Sun Microsystems Inc.
>
>
>
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Craig Twardy
Nortel Networks
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