Re: [SI-LIST] : How board over-shoot under-shoot influence a

Yehuda D. Yizraeli (yehuda@zoran.co.il)
Mon, 22 Mar 1999 11:52:44 +0200 (EET)

Charles, John.

Its interesting point to learn about, however the failures i am relating to are
short term, namely not related to reliability which make parameters different or so. According
to the current consumption, no latchup occour so it seems like changing the reference
of the input buffers or so and i can not understand how a glitch can do so (theoreticaly
it might happen, but with all chip self capacitance etc...?)

anyway, thanks!!

yehuda

>
> Yehuda,
>
> There are six distinct effects I can think of:
> 1. Excessive can cause latchup in CMOS (although not likely since latchup
> is usually controlled).
> 2. When there is no clamp diode to the supply rail, high E fields can
> create "hot carriers" in MOS devices which slowly degrade the device by
> permanently shifting the thresholds.
> 3. When there is a clamp diode to the substrate, if enough current is
> injected, the device becomes non-functional in the region around the
> substrate junction nearest the pad since it is forward biased. This occurs
> for a period of time, and then the device regains functionality.
> 4. High E fields on MOS gates can cause migration of impurities in poorly
> manufactured devices which leads to permanent threshold changes (shouldn't
> happen in today's devices).
> 5. High ringing means lots of reflections that persist over time. These
> reflections can affect subsequent switching and the exact timing of the edges.
> 6. Of course if the MOS gate, or PN junction is avalanched, then
> destruction can occur from excessive local heating.
>
> The high voltage of the spike occurs at very low current since the inputs
> are mostly capacitive.
>
> Charles Hill, consultant
> Alta Engineering
> chuckh@altaeng.com
>
>
> At 12:00 PM 3/21/99 +0200, Yehuda D. Yizraeli wrote:
> >Hello SI experts,
> >
> >
> > Its good design practice to have a non reflective board design, however i
> >would like to understand the nature of the failure caused by the reflections.
> >
> > One failure mechanism is double triggering, but assuming the reflections
> acuse
> >an overvoltage (over the power supply value, or under ground value) BUT
> not ringing through
> >thetriggering point, how can a chip be affected by this ringing....? Does
> it make the input
> >buffer levels lower (hey hey hey, its spikes, short term influence,
> doesn't it???).
> >
> >
> >
> > Any help, article and/or any pointer is appreciated.!!
> >
> >
> >
> >
> >
> >
> > regards, yehuda
> >
> >
> >
> >
> >
> >
> >--
> >-------------------------------------------------------------------
> > Yehuda D. Yizraeli
> >
> > Zoran Microelectronics Ltd. E-mail: yehuda@zoran.co.il
> > Advanced Technology Center Direct Tel: 972-4-85-45-795
> > P.O.B. 2495, Haifa 31204, Israel Operator : 972-4-85-45-777
> > http://www.zoran.com Fax : 972-4-8-551-550
> >-------------------------------------------------------------------
> >
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> >
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> >
> >The trouble with doing something right the first time is that
> >
> > nobody appreciates how difficult it was.
> >
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-- 
-------------------------------------------------------------------
   Yehuda D. Yizraeli

Zoran Microelectronics Ltd. E-mail: yehuda@zoran.co.il Advanced Technology Center Direct Tel: 972-4-85-45-795 P.O.B. 2495, Haifa 31204, Israel Operator : 972-4-85-45-777 http://www.zoran.com Fax : 972-4-8-551-550 -------------------------------------------------------------------

In god we trust, all the rest should use data

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

The trouble with doing something right the first time is that

nobody appreciates how difficult it was.

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****