Re: [SI-LIST] : The overshoot and undershoot criteria in PCI spec.

D. C. Sessions (dc.sessions@vlsi.com)
Tue, 12 Oct 1999 09:31:14 -0700

John Lin (=AAL=B4=C2=B7=D7) wrote:
>=20
> Dear all SI Experts,
>=20
> What are the overshoot and undershoot criteria for PCI 5V and 3.3V envi=
ronment?
> Based on PCI spec. rev. 2.2, 4.2.2.3 Section, Maximum AC Ratings and D=
evice Protection,
> for 3.3V PCI, the criteria seems to be 7.1V for overshoot and -3.5V for=
undershoot.
>=20
> For 5V PCI, 11V is for overshoot and -5.5V is for undershoot.
>=20
> I wonder that such big overshoot and undershoot voltages will affect th=
e reliability of chips even the voltages are within the spec.
>=20
> Your comments are appreciated.

First, it sounds like you're asking about overshoot, not undershoot. PCI
doesn't directly address ringback into the switching region. Assuming th=
at
you do mean "negative overshoot" where you wrote 'undershoot', then there
are parts to the answer.

1) PCI drivers, although absurdly strong for an unterminated environment,
*do* have their limits and you won't see 11 volts (or -5.5) even in a tot=
ally
unloaded PCI bus driven from one end.

2) The receivers, on the other hand, should be overspecified and thus the=
y
are required to tolerate Thevenin sources of that magnitude. Note, _Thev=
enin_
sources. There is a lower bound to the impedance of the source, which le=
ads
to:

3) PCI nodes are also required to have overshoot clamps. Thus, a current=
-limited
Thevenin source of 11 volts won't actually take a PCI node to 11 volts bu=
t to
a much more reasonable 6+ for a short time.

--=20
D. C. Sessions
dc.sessions@vlsi.com

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