Re: [SI-LIST] : Terminating a bidirectional bus

Daniel Roganti (droganti@lucent.com)
Tue, 04 May 1999 07:57:01 +0200

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Hello,

I'm curious about the method of termination you mentioned here below on
the SI List.
I have a situation similiar to this but there are several devices on the
bidirectinal bus(addr&data).
Would you have any more refereences on this type of termination ?
any info is much appreciated.
thanks,
Daniel Roganti

D. C. Sessions wrote:
>
> "Fox, Michael J" wrote:
> >
> > Arrigo,
> > I'd recommend looking at FPGA and SRAM's DC requirements carefully. A
> > series termination will cause a level shift. Unless you are using
> > reflective-mode transmission or the buffers are internally terminated, I'd
> > recommend parallel terminating both ends of the bus.
> > But that's only good if both chips have the same DC requirements. If they
> > have different DC requirements tell me about it and I'll give you that
> > lecture.
>
> All of the FPGAs that I've heard of have pure CMOS inputs with
> pullups (if available) optional. So level shift shouldn't be an
> issue. Also, the more complex ones give you the option of both
> CMOS inputs (rational) vs TTL emulation (silly).
>
> Actually, for a CMOS point-to-point connection you get surprisingly
> good results with a single resistor in the center of the trace.
>
> > -----Original Message-----
> > From: Arrigo Benedetti [mailto:arrigo@vision.caltech.edu]
> > Sent: Monday, May 03, 1999 9:21 AM
> > To: si-list@silab.eng.sun.com
> > Subject: [SI-LIST] : Terminating a bidirectional bus
> >
> > Dear all,
> >
> > I would like to know you opinion on this issue. I am interfacing a
> > state of the art FPGA with a high speed synchronous SRAM device. Since
> > the interface is bidirectional (the FPGA will read and write data to
> > the memory) I was wondering what is is the best way to terminate this
> > bus. My intuition is that if the data lines are not very long, then a
> > series termination near the FPGA end could have an effect similar to a
> > series termination near the memory end when the memory is driving the
> > bus.
> >
> > I've in the the standard SI book, and haven't found any hint on the
> > problem.
> >
> > thanks in advance
> >
> > -Arrigo Benedetti
> > --
> > Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu
> > Caltech, MS 136-93 phone: (626) 395-3695
> > Pasadena, CA 91125 fax: (626) 795-8649
> >

> --
> D. C. Sessions
> dc.sessions@vlsi.com
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