I think we are having a semantics problem regarding -Vcc to +2Vcc. My
comment was about your ", output swing might be -Vcc to +2Vcc and there
might be the non-linearities of clamps present." I interpreted "output
swing" to mean the AC swing of the part -- how far the part itself will
transition from high to low (or low to high). You seem to be using output
swing to characterize the voltage range the part must be able to tolerate
in an operating environment.
Sorry for the confusion.
If I remember (seems it was about 1967 or 68) the ECL arguments correctly
for 20-80% it gave a more realistic dv/dt. The 10-90% would have included
some very slow dv/dt areas that would give misleading numbers, slow, for
30-70% characterization would barely get the swing into the standard CMOS
Vih/Vil levels if at all. Since I don't know what logic family these
30-70% number came from it is hard to say how useful/useless they are.
From: Roy Leventhal [SMTP:Roy_Leventhal@mw.3com.com]
Sent: Monday, July 26, 1999 11:37 AM
Subject: RE: [SI-LIST] : Best type of models, edge rates & load
I believe you are correct in how the supply voltage is set up - whether
or simulated -. It is set at Vcc. But, the V-I curves are measured from
+2Vcc because that is the full range of incident + reflected voltage that
devices can see on a transmission line where reflection coefficient can run
-1 (short) to +1 (open). I recollect that a voltage source of -Vcc to
used to drive the I/O and the current into or out of the device is measured
The range of -Vcc to +2Vcc is much greater than the measurement conditions
historically pervailed when measuring (say) saturated switching times into
lumped, discrete, non-transmission line load. The accepted convention I
Fairchild and National in the early 1970's was 10% to 90% for
rise/fall/delay/storage time for any JEDEC registered 2N data sheet.
If you are correct about the 20% - 80% convention coming from Motorola it
an example of specsmanship supplanting accepted convention. Remember that
became roundly ignored by the semiconductor manufactuers (in that same time
period) because they found it "too constraining." It's only my opinion,
by time, but I recollect Motorola being in the lead in subverting the JEDEC
conventions. Semiconductor companies started issuing their own "registered"
(yeh, right!) data sheets that allowed them to, among other things, source
completely different die/mask set product lines (with VERY different
resitivities, etc., and VERY different Beta-Vs- Ic rolloff curves) so long
they met a few, fairly wide DC parameter windows. Talk about die shrink!
what, such substitutions sure didn't work in the actual designs.
So, what's your point about the 30% - 80% "transition time" convention
correctly point out that it's less than half the output swing? I can dig
data sheet and manufactuer's name for you if you wish. And yes, I think
pure specsmanship and quite misleading. If you just skim over the data
numbers well, Caveat Emptor.
But, I would guess that the 20% to 80% IBIS convention was chosen to fit in
more linear range of the I/O characteristics. I'm not sure that the choice
been a good one.
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