Thanks for your reply. I'm no device physicist but I don't
think Idsat should be a function of voltage. Certainly voltage
variation affects a CMOS buffer drive strength. However
I was asking for Idsat for the following equation relating drain current
to the gate-to-source voltage for a CMOS device in the ohmic region:
Also, I haven't been able to find the relationship between Idsat
and temperature in my text books.
BTW, for anyone else that wants to contribute - please don't
supply PROPRIETARY information that you have from foundrys that
you work with.
> HI Mike,
> You can expect a 4:1 variation over Process,voltage, and temperature for
3 sigma process models.
> Jim Freeman
> Mike Degerstrom wrote:
> > Can anyone tell me what reasonable Idsat variations one could
> > expect from a typical CMOS line? Could you please qualify your
> > answers such as "these are +/- 3 sigma numbers" if at all possible?
> > Mike
-- _______________________________________________________________ Mike Degerstrom Email: firstname.lastname@example.org Mayo Clinic 200 1st Street SW Gugg. Bldg. RM 1042A Phone: (507) 284-3292 Rochester, MN 55905 FAX: (507) 284-9171 WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html _______________________________________________________________
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