Re: [SI-LIST] : minimizing backplane clock jitter

D. C. Sessions ([email protected])
Mon, 03 May 1999 14:12:50 -0700

john lipsius wrote:
> All,
> I'm requesting recommendations on methods, specific vendors'
> chips, etc., to minimize jitter in backplane clock distribution.
> Currently,
> 1. backplane (copper only) distributes 80MHz clock point to point
> using LVDS driver & receiver for each load, from a central point
> that uses a sufficiently low jitter clock generator for Sonet.
> 2. Each receiving board uses the distributed clock (refclk) for a
> Sonet xcvr's refclk input and other loads.
> 3. We're using the Teradyne VHDM connector for the backplane conn.
> 4. sonet xcvr refclk input is LVTTL (Vil=.8v Vih= 2.0v).

You're pretty well hosed right there. LVTTL isn't tight enough
to meet SONET jitter specs anyway. (It's a little hard for me to
accept the idea of a SONET clock coming in single-ended in the first

D. C. Sessions
[email protected]

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