I assume this is a 6U daughtercard. The ground loops are a fact of life,
the idea is to minimize their area, so as to push the inductance down, and
the resonant frequency up. Those pins you are worrying about 9" away will
return minute amounts of the return signal current from the signal drivers
at the opposite end of your board. Those currents enclose a large loop
area, making efficient antennae. How much current the "distant" ground
pins return for "near" signals depends on the impedance distribution.
Since you are likely to have high speed edges on both P1 and P2, your only
choice is to try to keep the return inductance to a minimum everywhere.
Use lots of vias.
Preferably, there will be a ground via near every signal via everywhere on
the board, which includes the signal pins in P1 and P2. If you do not use
enough vias, then both your EMI and crosstalk will suffer.
At 04:57 PM 7/8/99 -0700, you wrote:
>I am designing a 10 layer VME board that has two edge connectors (P1 and
>P2). The connectors are about 4" long each with grounds distributed along
>the length of each connector.
>What is a good way to ground the two GND planes on our board?
>A) Simply ground each GND pin to both GND planes at the pin.
>B) Something else?
>The reason I'm thinking of this is because I can imagine a ground loop
>occurring between the outer GND pins of the connectors that are a total of
>about 9" away. My guess is that the simple approach will be fine, but I'm
>curious as to other opinions.
>Any suggestions would be greatly appreciated.
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