RE: [SI-LIST] : Edge rates

tomda (tom_dagostino@mentorg.com)
Thu, 15 Jul 1999 09:45:04 -0700

Besides the edge rate differences between different IC manufacturers, the
output impedance will differ significantly. Again using your ABT example,
the output impedance for National, TI and Philips are significantly
different in both the pull up and pull down characteristics. I have
measured many devices from all three of these ABT suppliers.

Another point of interest is the clamping characteristics within the same
family from different logic vendors. Some vendors of LVT have a good Vcc
clamp while another has a clamp that seems to disappear after 100 mV.

Tom Dagostino
ICX Modeling Group

-----Original Message-----
From: jaydiep@us.ibm.com [SMTP:jaydiep@us.ibm.com]
Sent: Thursday, July 15, 1999 7:25 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Edge rates

I appreciated Jan Vercammen sharing his edge rate data with the group; it's
nice
to have some real data that's without the usual marketing spin. One
caution
based on my own measurements is that one should not assume that logic
families
sourced from multiple suppliers will have the same characteristics. There
are
many different kinds of cross-license agreements that range from mask
sharing
(same circuit topology and device geometries, but may be different process)
to
only what I would call name-sharing (same DC specs. and prop. delays,
different
functions, and VERY different edge rates). To illustrate the latter case
using
ABT (an instance of name-sharing), which at least originally was built by
two
suppliers (TI and Philips), the rise and fall times for the one supplier's
parts
were at best half of those from the other. According to the one supplier,
their
engineers had designed edge rate control into their drivers, where the
other
supplier either had not, or had used different assumptions. Edge rates or
rise/fall times were not included in datasheets at that time, but have more
recently been included in some cases.

One also must worry about what happens when someone gets the idea to cost
reduce
the parts by building them in some new, smaller feature size IC process,
which
reduces device capacitance and therefore rise/fall times (without edge rate
control). I've been (as many other IBM designers have) an advocate of edge
rate
control for a long time, because at some point everything becomes a
transmission
line otherwise. Some circuit designers listen better than others.

Jay Diepenbrock

Senior Engineer
Interconnect Technology & Qualification
IBM Global Procurement, B8UA/061, RTP, NC
Phone: 919-543-8804 Fax: 919-543-3642
Email: jaydiep@us.ibm.com

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