Re: [SI-LIST] : [SI-LIST]:Drivers to minimize reflections

sweir (weirsp@a.crl.com)
Thu, 09 Sep 1999 01:26:46 -0500

Bobby,

It sounds like you are interfacing to either MVIP or SCSA parts. If so,
then clock skew is not a major issue as those protocols follow master-slave
timing.. The cheap and "impure" solution is to load the driver output with
an RC network to slow the risetime down to about 1nS / inch of load
trace. Typical resistor values are in the 10 - 30 ohm range. This works
well up to about 10-15nS risetimes. You need to make sure that your
receiving devices can tolerate the resulting soft clocks. If you do this,
it is still a good idea to daisy-chain route the traces in question. If
you cannot tolerate slowing the clock edge to 1nS / inch, then you can
still slow the edge with an RC network, and then end-terminate the
track. As clumsy as this technique is, it is pretty effective for both SI
and EMC. Almost any 3V family will work with this, such as garden variety
LVC, or ALVC.

If you are interfacing to something else, then you need to know what your
clock skew budget is between devices. It doesn't matter how slow your
clock is. If the devices both update their outputs and sample with the
same clock edge, then the clock routing creates a race with the data
outputs from one device to another. This will largely determine what
routing is appropriate, which in-turn constrains the drive and termination
scheme.

Regards,

Steve.
At 12:41 PM 9/8/99 -0500, you wrote:
>Dear SI gurus,
>I am designing a board (approx. 6"x8.5") that has a number of buffered
>signals. The critical signals have a relatively high fanout (up to about
>20) that go all over the board. My goal is to eliminate
>reflections/glitches in these signals which could cause double-clocking.
> Is my best approach to look for a slow edge rate device (not incredibly
>fast signals here, i.e. 2MHz clock lines) to allow me to treat the loads as
>a lumped-load which doesn't require terminations? Or am I better off
>splitting the line and terminating each signal? If I split it enough, I
>can do point-to-point with series terminations on each line, but this will
>use more board space. Or I can do it point-to-multipoint, grouping the
>loads that are physically near each other and adding an RC termination at
>the end of each group.
>
>BTW, signal levels are 3.3V. Any particular logic family ideally suited
>for this job?
>
>
>Thanks in advance,
>Bobby Hubertus
>Design Engineer
>BBS Telecom
>bobbyh@bbstelecom.com
>
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