si-list.mail by subject
Starting: Wed 06 Dec 1995 - 11:37:40 PST
Ending: Sun 20 Jun 1999 - 03:56:60 PST
Messages: 2087
- (Differential SCSI)
- (Fwd) Buried Capacitance
- (Fwd) RE: [SI-LIST] : IC input impedance
- (no subject)
- +3.3,5-board stackup problem
- +3.3,5-board stackup problem / return currents...
- 1GB/s serial Diff Pairs over Backplanes and Connectors
- 2 Job Postings
- 3.3V/5V planes
- [Fwd: [SI-LIST] : IBIS AND EMC]
- [Fwd: [SI-LIST] : Schottky diode termination]
- [Fwd: Interfacing Sync DRAMs]
- [old] Differential Reflection Question
- [SI-LIST] (transmission line demo tool)
- [SI-LIST] - Design Note
- [SI-LIST] - MECL inform
- [SI-LIST] - Overshoot/U
- [SI-LIST] : �^�� : [SI-LIST] : stackup impedance.
- [SI-LIST] : "Bob Smith" Termination
- [SI-LIST] : "Home Made TDR"
- [SI-LIST] : "Picket Fence" (Via Fence) for increasing isolation between
- [SI-LIST] : (unknown chars) : [SI-LIST] : stackup impedance.
- [SI-LIST] : 2 great Signal Fidelity positions open at Stratus!!!
- [SI-LIST] : 3.3V Design
- [SI-LIST] : 4 March 98 Meeting, Tech Soci NepconWest (Anaheim, Calif)
- [SI-LIST] : 440BX IBIS model (help find)
- [SI-LIST] : 5v and 3.3v
- [SI-LIST] : 66 MHz AGP Clock Signal
- [SI-LIST] : 9/18/97 - IBIS FORUM - EAST Agenda & Directions
- [SI-LIST] : =?iso-8859-1?Q?=BB=D8=B8=B4:_=5BSI-LIST=5D_:_A_timing_question_in_hig?=
- [SI-LIST] : =?iso-8859-1?Q?=BB=D8=B8=B4?=: [SI-LIST] : A timing
- [SI-LIST] : =?ISO-8859-1?Q?[SI-LIST]:_2nd_IEEE_Workshop_=22Signal_Propagation_on_Interconnects=22?=
- [SI-LIST] : =?ISO-8859-1?Q?[SI-LIST]:_Premiere_course_on_=22Circuit_Simulation_and_Signal_Integrity=
- [SI-LIST] : ?Dumb Question Regarding Multilayer Boards
- [SI-LIST] : [Fwd: (no subject)]
- [SI-LIST] : [MODEL CREATION]
- [SI-LIST] : [SI-LIST]: [MODEL CREATION] & IBIS models
- [SI-LIST] : [SI-LIST]:S,R,Z, I logic states
- [SI-LIST] : A 10 layer stackup
- [SI-LIST] : A timing question in high speed bus
- [SI-LIST] : A/D and D/A Converters PWR/GND Connection
- [SI-LIST] : About multilayer Board
- [SI-LIST] : AGENDA EUROPEAN IBIS SUMMIT 2/26/98
- [SI-LIST] : AGP Buffer strengths
- [SI-LIST] : AGP impedance compensated drivers?
- [SI-LIST] : Allowable crosstalk on VGA signals to monitor on PC ?
- [SI-LIST] : Also, Er vs. freq.
- [SI-LIST] : Alternative viewer for Hspice .ac0,.tr0,.sw0 files
- [SI-LIST] : AMPredictor
- [SI-LIST] : An update on the IBIS East meeting for 18 September, 1997
- [SI-LIST] : another stack-up question
- [SI-LIST] : Another trace-Z question
- [SI-LIST] : Ansoft 2D extractor question
- [SI-LIST] : Ansoft HFSS Technical Workshop, May 14, 15
- [SI-LIST] : Ansoft SI seminar coming soon
- [SI-LIST] : ANY EXPERIENCE OF MENTOR'S IS TOOLS
- [SI-LIST] : Apology
- [SI-LIST] : ASIC noise update....
- [SI-LIST] : attenuation calculations
- [SI-LIST] : Authors Wanted
- [SI-LIST] : Backplane Analysis / GTL Technology
- [SI-LIST] : Backplane connectors for Fibre Channel
- [SI-LIST] : BackPlane stackup
- [SI-LIST] : Backplanes, connectors, cables - Simulating?
- [SI-LIST] : bare board resonance test
- [SI-LIST] : bga
- [SI-LIST] : BGA Ni-Au platting pattern.
- [SI-LIST] : Board Stack-up
- [SI-LIST] : Book for sale
- [SI-LIST] : Book on RF Package Modeling
- [SI-LIST] : Books
- [SI-LIST] : Books (Montrose, Johnson)
- [SI-LIST] : Breaking the silence: EMI/EMC "QUIET" users?
- [SI-LIST] : Buried Capacitors
- [SI-LIST] : Burst noise simulation
- [SI-LIST] : Bus bar current carrying capability
- [SI-LIST] : bypass cap question (long, simple)
- [SI-LIST] : cable grounding
- [SI-LIST] : Cable skew
- [SI-LIST] : Calculating Trace Inductance
- [SI-LIST] : call for papers - PCB West
- [SI-LIST] : CALL FOR PAPERS, 2nd International Workshop on SIGNAL
- [SI-LIST] : CALL FOR PAPERS: 1998 IEEE Radio and Wireless Conference (RAWCON'98) (Fwd)
- [SI-LIST] : Call for participation: Workshop on Signal Propagation in Interconnects
- [SI-LIST] : Can floating data bus cause DRAM soft errors?
- [SI-LIST] : Career Opportunity
- [SI-LIST] : Cautious offer to test....
- [SI-LIST] : CBT for Signal Integrity
- [SI-LIST] : Challenging Signal Integrity Engineer Positions @ Stratus!
- [SI-LIST] : Characteristic impedance
- [SI-LIST] : Clock and Transmission Line Termination
- [SI-LIST] : Clock chip supply voltage
- [SI-LIST] : Clock skew
- [SI-LIST] : Clock tree
- [SI-LIST] : Clock Verification Seminar
- [SI-LIST] : CMOS off-chip driver design
- [SI-LIST] : Complex Planes
- [SI-LIST] : Conducted EMC Testing of PLL jitter
- [SI-LIST] : conductor thickness versus current
- [SI-LIST] : Confidential Search for Sr Signal Integrity Engineer
- [SI-LIST] : Contact Current Rating ?
- [SI-LIST] : Controlled impedance in Flex Circuit
- [SI-LIST] : Controlled Z PCB's
- [SI-LIST] : Convert an IBIS model to SPICE Model.
- [SI-LIST] : correction : bypass cap question (long, simple)
- [SI-LIST] : Cross section geometry for the previous post on inductance
- [SI-LIST] : Cross-talk Concerns
- [SI-LIST] : crosstalk through resistor networks?
- [SI-LIST] : Crosstlak in ultra high speed pcb
- [SI-LIST] : Crow bar current (dc switching current) vs power
- [SI-LIST] : Crystal Oscillator Vs Resonator
- [SI-LIST] : Crystal Question
- [SI-LIST] : curve tracers and Output Impedance
- [SI-LIST] : D/A and A/D Connections
- [SI-LIST] : daisy chain
- [SI-LIST] : data bus clash - how bad?
- [SI-LIST] : DEC 4, 1997 - IBIS User Group Meeting, Additional Topic
- [SI-LIST] : Decomposing PCB elements for RF(ish) applications
- [SI-LIST] : Decoupling capacitor selection & placemen
- [SI-LIST] : Decoupling capacitor selection & placement
- [SI-LIST] : Decoupling capacitors
- [SI-LIST] : Decoupling Caps and Return Currents
- [SI-LIST] : Decoupling:routing
- [SI-LIST] : Definition for rise time?
- [SI-LIST] : delay lines
- [SI-LIST] : Design Note on Right Angle Bends
- [SI-LIST] : Determining CMOS Cin with TDR methodology
- [SI-LIST] : Dielectric Constant
- [SI-LIST] : Dielectric loss
- [SI-LIST] : Dielectric withstand voltage requirements
- [SI-LIST] : Dieletric Constant Polyimide
- [SI-LIST] : Diff measurements with VNA
- [SI-LIST] : Differential Clock Routing
- [SI-LIST] : Differential Clocking & Guard Trace
- [SI-LIST] : Differential impedance
- [SI-LIST] : differential pairs
- [SI-LIST] : Differential Pairs - Different Approach
- [SI-LIST] : Differential pairs and place splits
- [SI-LIST] : Differential Reflection Question
- [SI-LIST] : Differential SCSI BP design
- [SI-LIST] : Differential Signals
- [SI-LIST] : Digital Interconnect Position at HP
- [SI-LIST] : Dinner mtg 26sept97, Los Angeles area
- [SI-LIST] : Diode Termination of Transmission Lines
- [SI-LIST] : diode terminations(?)
- [SI-LIST] : Diodes, EMC, ESD Protection networks
- [SI-LIST] : Directions/Agenda for 2/12/98 IBIS Users' Forum
- [SI-LIST] : Disconnect Requests Sent to si-list
- [SI-LIST] : Dispersive interconnects and skin effect
- [SI-LIST] : Do you have a web site for signal integrity
- [SI-LIST] : Do you have a web site for signal integrity stuff?
- [SI-LIST] : Does IBIS describe output transition which both
- [SI-LIST] : Does IBIS describe output transition which both MOS turned on?
- [SI-LIST] : Does IBIS describe output transition which both MOS turned on?
- [SI-LIST] : Does solder mask reduce trace impedance ?
- [SI-LIST] : Does SSO make outputs earlier as well as later?
- [SI-LIST] : Does SSO make outputs earlier as well as later? YES, BUT...
- [SI-LIST] : Down-bond in chip packaging
- [SI-LIST] : Driver Strength
- [SI-LIST] : Dual Stripline impedance
- [SI-LIST] : Earth Ground
- [SI-LIST] : Earth Ground]
- [SI-LIST] : Eastern IBIS Kickoff Meeting Sept 18
- [SI-LIST] : EDA suite for Win NT
- [SI-LIST] : EDE opportunities at Sun
- [SI-LIST] : EDN SI tool
- [SI-LIST] : Effective Dielectric
- [SI-LIST] : Effective terminating voltage
- [SI-LIST] : Electrical Package Characterization Engineer
- [SI-LIST] : Embedded microstrip calculations, Ultracad Calculator
- [SI-LIST] : EMC Issues with ASIC design
- [SI-LIST] : EMC Society Meeting Notice, Sunnyvale, CA
- [SI-LIST] : EMC Symposium
- [SI-LIST] : EMC-98, 1 June, Santa Clara CA
- [SI-LIST] : EMI
- [SI-LIST] : EMI idea or heresy
- [SI-LIST] : EMI Measurement
- [SI-LIST] : End launch SMA connectors
- [SI-LIST] : EPEP'97 ADVANCED PROGRAM
- [SI-LIST] : Er vs T
- [SI-LIST] : EUROPE IBIS SUMMIT MEETING
- [SI-LIST] : EUROPEAN IBIS SUMMIT - 2nd Call
- [SI-LIST] : EUROPEAN IBIS SUMMIT ANNOUNCEMENT
- [SI-LIST] : Evaluation of Vendor tools on SI list
- [SI-LIST] : Evaluation of Ventor Tools
- [SI-LIST] : Excellent Reference Book
- [SI-LIST] : Excessive clock overshoot
- [SI-LIST] : Excessive clock overshoot]
- [SI-LIST] : Expression for inductance of a flat conductor
- [SI-LIST] : Extraction of mutual inductance and mutual capacitance from VNA
- [SI-LIST] : eye patterns
- [SI-LIST] : Ferrite Beads in HSPICE
- [SI-LIST] : Fibre-Channel Equaization Circuits
- [SI-LIST] : field solver for differential pairs
- [SI-LIST] : Final report on inductance vs. frequency
- [SI-LIST] : FIXED: curve tracers and Output Impedance
- [SI-LIST] : Flyback Transformer Model
- [SI-LIST] : Focusing on Parasitic Parameters
- [SI-LIST] : Focusing on Parasitic Parameters and ISI
- [SI-LIST] : Formulas for Calculating PTH Capacitance
- [SI-LIST] : Freq. dependent losses in Spice?
- [SI-LIST] : from SPICE to EDIF
- [SI-LIST] : Future bus backplane
- [SI-LIST] : FW: SI Engineer position
- [SI-LIST] : FW: signal isolation, RF board
- [SI-LIST] : Fwd: Connector question on SI
- [SI-LIST] : Fwd: EMI/SI Job Opening @Ridge Technologies
- [SI-LIST] : FWD: Short Courses in Applied CEM
- [SI-LIST] : Fwd:Allowable crosstalk on VGA signals to monito
- [SI-LIST] : GND plane heat dissipation
- [SI-LIST] : Great Opportunity @Sun
- [SI-LIST] : Ground bounce caused by VMEbus transceivers
- [SI-LIST] : Ground bouncing ???
- [SI-LIST] : GTLP16612 Termination
- [SI-LIST] : Guard banding
- [SI-LIST] : Guard Trace Effect on Impedence
- [SI-LIST] : HF SCSI connectors
- [SI-LIST] : High freq. mag. prop. of Kovar
- [SI-LIST] : High Permittivity Board Level Decoupling and
- [SI-LIST] : High Permittivity Board Level Decoupling and related issues
- [SI-LIST] : High Speed Design method
- [SI-LIST] : High Speed Design Symposium
- [SI-LIST] : High Speed Queries
- [SI-LIST] : Horror stories ?
- [SI-LIST] : How substrate noise influence input levels..???
- [SI-LIST] : How to construct guard bands in Ansoft 2D
- [SI-LIST] : How to do correlation with two extra Rising/Falling waveforms?
- [SI-LIST] : How to estimate total layers needed or trace
- [SI-LIST] : How to estimate total layers needed or trace pitch?
- [SI-LIST] : How to identify SSO
- [SI-LIST] : How to identify SSO groups?
- [SI-LIST] : How to measure MOS capacitance
- [SI-LIST] : How to model chip to SDRAM pc board
- [SI-LIST] : HSPICE to QUAD models
- [SI-LIST] : Hyperlynx IBIS Developer Tool Kit - Action Item from IBIS User
- [SI-LIST] : IBIS Accuracy Sub-Committee Minutes
- [SI-LIST] : IBIS AND EMC
- [SI-LIST] : IBIS delay line model
- [SI-LIST] : IBIS Meeting September 18th
- [SI-LIST] : IBIS model question
- [SI-LIST] : IBIS Model Verification
- [SI-LIST] : IBIS Model Verification (correction)
- [SI-LIST] : IBIS Modeling
- [SI-LIST] : IBIS models
- [SI-LIST] : IBIS to Spice
- [SI-LIST] : IBIS User Forum Meeting Minutes - 2/12/98
- [SI-LIST] : IBIS User Group Meeting - Dec. 4, 1997
- [SI-LIST] : IBIS User Group Meeting - LOCATION/DIRECTIONS
- [SI-LIST] : IBIS user group meeting minutes - 1/18/98
- [SI-LIST] : IBIS User Group Meeting Reminder - Thurs., 3/19/98, 3:00 PM
- [SI-LIST] : IBIS User Group minutes 3/19 - In future will only be sent to
- [SI-LIST] : IBIS User Group Sub-Committee
- [SI-LIST] : IBIS USER Meeting - 3/19/98, 3:00PM, at DEC, Hudson, MA
- [SI-LIST] : IBIS User Meeting - Jan. 15, 1998 at 3:00pm
- [SI-LIST] : IBIS Version 3.0
- [SI-LIST] : ibis,si-list,looking for ibis models
- [SI-LIST] : IC DIE SHRINK
- [SI-LIST] : IC input impedance
- [SI-LIST] : IEEE (where to find them freely on the web?)
- [SI-LIST] : IEEE EMC meting, SF Bay Area
- [SI-LIST] : IEEE EMC Symposium - Denver 1998
- [SI-LIST] : IMAPS - OC meeting 22 jan, Micro Vias
- [SI-LIST] : Impedance of micro-strip over wide ground trace
- [SI-LIST] : Incorporating 3-d passive circuit models into
- [SI-LIST] : Incorporating 3-d passive circuit models into SPICE
- [SI-LIST] : Inductance vs. frequency
- [SI-LIST] : Intelligent Placement of Decoupling Capacitors
- [SI-LIST] : Interesting si-list statistics
- [SI-LIST] : internal layer routing and EMI issues
- [SI-LIST] : Is feedback really EVIL?
- [SI-LIST] : Jitter Measurement
- [SI-LIST] : job opening
- [SI-LIST] : JOB POSTING
- [SI-LIST] : JOB POSTING : Signal Integrity Engineer
- [SI-LIST] : Job Postings on si-list
- [SI-LIST] : looking for "CMOS Simultaneous Switching Noise"
- [SI-LIST] : Looking for corner PCI spice models
- [SI-LIST] : Looking for SI consultants in the North East
- [SI-LIST] : Looking for Signal Integrity Engineers
- [SI-LIST] : Lossy lines,TDR and connectors
- [SI-LIST] : low-cost 2-D field solver
- [SI-LIST] : Lowering ASIC noise
- [SI-LIST] : Making trace impedance tolerance range
- [SI-LIST] : Mass: Signal Integrity/Timing 6+ Month Contract
- [SI-LIST] : measuring CMOS Cin with HP4275A
- [SI-LIST] : Measuring Ground Noise
- [SI-LIST] : Measuring PLL jitter
- [SI-LIST] : MECL Book
- [SI-LIST] : MECL book+ribbon cable
- [SI-LIST] : MECL information
- [SI-LIST] : Meeting Announcement, SoCal98, Anaheim, 12May98
- [SI-LIST] : method for identifying Xtalk and SSO noise ?
- [SI-LIST] : microwave radiation due to network analyzers
- [SI-LIST] : Miller Capacitance
- [SI-LIST] : Minutes from IBIS Forum User's Meeting 12/4/97
- [SI-LIST] : Minutes from IBIS-East Forum kickoff meeting
- [SI-LIST] : Mixed signal - PWR and GND configuration issue
- [SI-LIST] : model translation
- [SI-LIST] : Modeling BGAs with floating ground plane
- [SI-LIST] : Modeling connector pin vias
- [SI-LIST] : Modeling Package parasitics
- [SI-LIST] : models page on http://www.eia.org/eig/ibis/ibis.htm
- [SI-LIST] : More on differential impedance calculations
- [SI-LIST] : more on pcb stack-ups
- [SI-LIST] : mpc68360 Motorola IBIS models
- [SI-LIST] : MPI: Metalized Particle Interconnect
- [SI-LIST] : Multi-wire boards
- [SI-LIST] : My Resume..
- [SI-LIST] : need accurate diode model at low current
- [SI-LIST] : need new BGA vendor
- [SI-LIST] : Need your comments in selection of SI simula
- [SI-LIST] : Need your comments in selection of SI simulation tool!
- [SI-LIST] : Net topology, reflection cancellation ?
- [SI-LIST] : New 3-D Inductance Extraction Software : CAPRI3D
- [SI-LIST] : New Book: "Digital Systems Engineering" by Dally and Poulton
- [SI-LIST] : New VME Backplane -- Star Layout
- [SI-LIST] : newbye
- [SI-LIST] : No subject given
- [SI-LIST] : Non-ideal return current paths
- [SI-LIST] : NOTE 03/30/98 16:24:58
- [SI-LIST] : OFF TOPIC: Junk Mail and what to do with it
- [SI-LIST] : On-board Switching Power Supply
- [SI-LIST] : Open position - Viewlogic Europe
- [SI-LIST] : Open positions at MCNC
- [SI-LIST] : Opening at Dell
- [SI-LIST] : OPENING: Signal Integrity Engineer, Juniper Networks
- [SI-LIST] : Opportunity at Dell
- [SI-LIST] : Oscillator or Crystal
- [SI-LIST] : Other materials for GHz application
- [SI-LIST] : Output Driver Impedance Variation?
- [SI-LIST] : Output driver versus internal logic switching noise
- [SI-LIST] : Output Impedance
- [SI-LIST] : Output shorted to Ground!
- [SI-LIST] : overshoot
- [SI-LIST] : Overshoot/Undershoot
- [SI-LIST] : Overshoot/Undershoot:
- [SI-LIST] : Package design position
- [SI-LIST] : Package prices and circuit elements values
- [SI-LIST] : Parasitics + timing (any idea)
- [SI-LIST] : passive cable equalization network
- [SI-LIST] : PC Choice
- [SI-LIST] : PCB Benchmark '98
- [SI-LIST] : PCB Bennchmark '98
- [SI-LIST] : PCB Build
- [SI-LIST] : PCB design company
- [SI-LIST] : PCB design rules for Ultra 2 SCSI SE / LVD differential lines.
- [SI-LIST] : PCB design techniques for EMC control
- [SI-LIST] : PCB parameters
- [SI-LIST] : PCB Pwr Planes
- [SI-LIST] : PCB Stacking!
- [SI-LIST] : PCB track length and ringing
- [SI-LIST] : PCI Slew Rate Test Load
- [SI-LIST] : Pinout of 2mm HM Backplane Connector
- [SI-LIST] : Placement of series termination
- [SI-LIST] : PLD/FPGA folks
- [SI-LIST] : Polylines conversion for Maxwell SI Solver
- [SI-LIST] : Position Available,
- [SI-LIST] : positions
- [SI-LIST] : Positions Available
- [SI-LIST] : Power Plane Thickness
- [SI-LIST] : power supply filtering and bypassing
- [SI-LIST] : Power Supply Noise Filters
- [SI-LIST] : Power-Down effect on power supply voltage and Clocks
- [SI-LIST] : Power-plane resonance article
- [SI-LIST] : Power/Ground Decoupling Methods?
- [SI-LIST] : Power/ground plane models
- [SI-LIST] : Precision Clocking
- [SI-LIST] : Preferred PWB impedances
- [SI-LIST] : Printed Circuit Design's 1999 Editorial Calendar
- [SI-LIST] : Priority of test pads
- [SI-LIST] : Proactive SI Engineering
- [SI-LIST] : Propagation velocity / discontinuous referen
- [SI-LIST] : Propagation velocity / discontinuous reference
- [SI-LIST] : Propagation velocity / discontinuous reference pl ane
- [SI-LIST] : Propagation velocity / discontinuous reference plane
- [SI-LIST] : Proposal for an IBIS Accuracy Specification
- [SI-LIST] : QUAD Model & Device capacitance
- [SI-LIST] : query
- [SI-LIST] : Question about Gear vs Trapezoidal methods for simulations within HSPICe
- [SI-LIST] : RC terminations on multidrop busses
- [SI-LIST] : RE:
- [SI-LIST] : RE: (transmission line demo tool)
- [SI-LIST] : RE: AGP impedance compensated drivers?
- [SI-LIST] : RE: Differential impedance
- [SI-LIST] : RE: Freeware for demonstration of transmission line reflections
- [SI-LIST] : RE: IBIS Open Forum minutes of 12/5
- [SI-LIST] : RE: MODEL CREATION
- [SI-LIST] : RE: Models & EDA Vendors
- [SI-LIST] : RE: RC terminations on multidrop busses
- [SI-LIST] : RE: Schottky diode termination
- [SI-LIST] : RE:Termination of High Speed Bus
- [SI-LIST] : Re[2]: IBIS connector models
- [SI-LIST] : Regular Full-time Technical Positions
- [SI-LIST] : Relative permeability of KOVAR
- [SI-LIST] : Reliability Forums
- [SI-LIST] : REPOST: Breaking the silence - EMI/EMC "QUIET" users?
- [SI-LIST] : Request to SI list Administrator
- [SI-LIST] : resistor models
- [SI-LIST] : resume - signal integrity engineer
- [SI-LIST] : Rev -1 Eastern IBIS Kickoff Meeting Sept 18
- [SI-LIST] : RF experience VS SI issues
- [SI-LIST] : Santa Clara Valley Chapter meeting
- [SI-LIST] : Schiffman phase shifters
- [SI-LIST] : Schottky diode termination
- [SI-LIST] : Screened/Shielded UTP Cabling
- [SI-LIST] : Seeking T-Tech Quick-Circuit used equipment
- [SI-LIST] : Selection of Optimum Termination
- [SI-LIST] : Self and mutual inductance
- [SI-LIST] : Self-inductance
- [SI-LIST] : Sensitive Info on si-list
- [SI-LIST] : Serpentine traces
- [SI-LIST] : Short Course - 2nd announcement
- [SI-LIST] : SI Consulting Opportunity in Silicon Valley
- [SI-LIST] : SI Engineer
- [SI-LIST] : SI engineer available
- [SI-LIST] : SI in cells.
- [SI-LIST] : SI Models Creation
- [SI-LIST] : SI models creation.
- [SI-LIST] : SI opening - EMC
- [SI-LIST] : SI openings at Stratus -- ... last one
- [SI-LIST] : SI openings at Stratus else delete
- [SI-LIST] : SI openings at Stratus else delete -- OBJECT
- [SI-LIST] : SI openings at Stratus else delete -- OBJECTIONS ...
- [SI-LIST] : SI Software
- [SI-LIST] : SI University programs
- [SI-LIST] : SI-LIST
- [SI-LIST] : Si-List administrative trivia
- [SI-LIST] : si-list archive temporarily unavailable
- [SI-LIST] : si-list archives
- [SI-LIST] : si-list archives restored
- [SI-LIST] : si-list software modification
- [SI-LIST] : Signal Ground at the connector
- [SI-LIST] : Signal Integrity Conference in Singapore
- [SI-LIST] : Signal Integrity Engineer Position Available
- [SI-LIST] : Signal Integrity Engineering opportuinities at Intel Corp.
- [SI-LIST] : Signal Integrity In General
- [SI-LIST] : Signal Integrity of 500 MHz on PCB
- [SI-LIST] : Signal Integrity Position
- [SI-LIST] : Signal Integrity position available
- [SI-LIST] : Signal Integrity position open at 3Com
- [SI-LIST] : Signal Integrity Positions
- [SI-LIST] : Signal integrity simulation tool - your opinion a nd recommandation
- [SI-LIST] : Signal integrity simulation tool - your opinion and recommandation
- [SI-LIST] : Signal Integrity/Board design
- [SI-LIST] : signal level conversions
- [SI-LIST] : Simulating Tools
- [SI-LIST] : Single-ended SCSI vs. di
- [SI-LIST] : Single-ended SCSI vs. differential SCSI
- [SI-LIST] : skin effect and transmission line simulators
- [SI-LIST] : Skin effect Modeling and Verification
- [SI-LIST] : Slew rate
- [SI-LIST] : SMA Impedance Matching
- [SI-LIST] : software development position at Cadence
- [SI-LIST] : Software Engineering position at Mayo Medical Center
- [SI-LIST] : Some issues about fineline BGA ..
- [SI-LIST] : Some questions about capacitor reliability
- [SI-LIST] : Speaker sought
- [SI-LIST] : SPICE Buffer Models
- [SI-LIST] : SPICE for SI analysis
- [SI-LIST] : Spice Mode for Emacs
- [SI-LIST] : SPICE Models
- [SI-LIST] : SPICE or IBIS SI models
- [SI-LIST] : Split vs. common chip busses
- [SI-LIST] : SSO - How simultaneous is simultaneous?
- [SI-LIST] : SSO : How to identify SSO groups?
- [SI-LIST] : SSO in ASICs
- [SI-LIST] : SSO noise: Through current vs. Discharge current
- [SI-LIST] : stackup impedance.
- [SI-LIST] : stackup question
- [SI-LIST] : Standard Component Data Sheet
- [SI-LIST] : Standard PCI load
- [SI-LIST] : Stratus looking for Signal Fidelity Engineers
- [SI-LIST] : Substrate modeling
- [SI-LIST] : Substrate modeling and analysis tool
- [SI-LIST] : Surface Mount Cap Lead Inductance
- [SI-LIST] : Sweeping Temp within MonteCarlo in HSPICE
- [SI-LIST] : Switching current and pull-down current
- [SI-LIST] : Switching Current in a high-speed digital pcb: How to calculate
- [SI-LIST] : Synchronous SRAM Application
- [SI-LIST] : TDR analysis
- [SI-LIST] : TDR Analysis: Layer Peeling Algorithm using Matlab
- [SI-LIST] : TDR formula
- [SI-LIST] : TDR Measurements
- [SI-LIST] : TDRs and frequency domain
- [SI-LIST] : Teaching SI
- [SI-LIST] : Termination and Test Equipment leads
- [SI-LIST] : Termination for bi-directional lines
- [SI-LIST] : Terminations scheme for bi-directional bus
- [SI-LIST] : Test Message (delete before reading:)
- [SI-LIST] : TestPad R,L,C
- [SI-LIST] : Text Book in SI
- [SI-LIST] : Thanks for responding my solder mask question.
- [SI-LIST] : The Flight-Time/SI Effects of Trace 'Trombon
- [SI-LIST] : The Flight-Time/SI Effects of Trace 'Tromboning'
- [SI-LIST] : timing design tool
- [SI-LIST] : To overshoot or undershoot: ( to diode or not to diode)
- [SI-LIST] : Trace impedance
- [SI-LIST] : Trace impedance measurement for dual stripline
- [SI-LIST] : Training course in SPICE
- [SI-LIST] : Transmission Line Analysis Software
- [SI-LIST] : Transmission Line Conductors
- [SI-LIST] : Transmission line model in Pspice
- [SI-LIST] : Transmission Line Theory
- [SI-LIST] : twisted pair attenuation
- [SI-LIST] : tying clock outputs to reduce skew?
- [SI-LIST] : Types of Bypass Caps
- [SI-LIST] : uBGA high frequency characteristics
- [SI-LIST] : UltraCAD Calculator
- [SI-LIST] : UltraCAD needs 2 designers
- [SI-LIST] : UltraCAD needs another designer
- [SI-LIST] : UltraCAD PCB Transmission Line Calculator
- [SI-LIST] : Unconnected headers and connectors
- [SI-LIST] : UnNamed
- [SI-LIST] : update on measuring CMOS Cin with HP4275A
- [SI-LIST] : USB differential lines.
- [SI-LIST] : USB modeling
- [SI-LIST] : via/pad capacitance and resistance
- [SI-LIST] : viewing HSPICE results without awaves
- [SI-LIST] : Virtual o-scope simulation models
- [SI-LIST] : VMEbus transceivers
- [SI-LIST] : W-element Simulation
- [SI-LIST] : Worst case VI curve for PCI spec a reality?
- [SI-LIST]: SSO noise: Through current vs. Discharge current]
- admin test message
- Alloy-42
- animation program to show travelling wave
- Announcement of Short Course
- Announcement: si-list server to be off net for several days
- Ansoft mesh generation
- Ansoft Seminar Series this week
- ANTEM'96
- Archive required
- ASIC Design Positions @ Packet Engines!!!
- ASIC DESIGNER: case temperature OR ambient temperature...?
- ASSY: GEN: Popcorning during reflow
- ATM positions in Dallas
- attenuation calculations
- AW: [SI-LIST] : Burst noise simulation
- AW: [SI-LIST] : High Permittivity Board Level Decoupling and rela ted
- AW: [SI-LIST] : How to measure MOS capacitance
- AW: AW: [SI-LIST] : Burst noise simulation
- Board-Level Design Engineer Position at Silicon Graphics
- Buried Capacitance
- Cable Skew
- CAD Engineer Position
- CAD Engineer Position Available
- Call for Papers ( EM Simuation Tools )
- Call for Papers - IEEE ISIS'97
- Circuit Design Consultant
- CMOS off-chip driver design
- Commercial Postings/Advertising on si-list
- Comp overstress
- component over-stress
- component overstress
- Confer. on wireless comm.
- Connector pinout question
- Connectors and cables for high-speed digital signals
- continously variable delay line avail?
- Controlled Impedance Connectors
- Controlled impedance in Flex Circuit
- Coupled Line Program available via anonymous ftp
- Coupled Trans. Line Spice subckt generator program
- CROSS-TALK
- decoupling/ bypass capacitors at connectors
- Delay line
- delay lines with PCB traces
- Delete from mailing list
- Design Engineers wanted in Pacific NW!
- Determining CMOS Cin with TDR methodology
- did you receive this via si-list ??
- dielectric loss
- Diff Skew
- Differential clock
- Differential impedance
- Differential Pair Skew
- DIFFERENTIAL ROUTING-- what to do? --
- Differential SCSI
- Dinner mtg 26sept97 s/b25th
- Does solder mask reduce trace impedance ?
- drivers, recivers and power planes
- Dual stripline
- Dual Stripline impedance
- Electrical Package Characterization Engineer
- Electromechanical relays
- Embedded microstrip calculations, Ultrac...
- Embedded microstrip calculations, Ultracad Calculator
- EMC-98, 1 June, Santa Clara CA
- Errata for book: "Digital Circuits Electrical Design" by Ron K. Poon
- Example ECL driver/receiver model
- eye pattern reading
- eye patterns
- FAQ request
- Fast TR
- FCT806 Clock Driver
- Focussed on USING BC..
- Formula for Via Self-Capacitance and Self-Inductance
- Formulas for Crosstalk Calculation PCB traces
- FORWARDED from si-admin: Buried Capacitance
- FS: Book (numerical electromagnetics)
- ftp'ing new Hspice's t-line model
- FW: [SI-LIST] : Contact Current Rating ?
- FW: [SI-LIST] : Dielectric loss (Intuitive explanation)
- FW: [SI-LIST] : FIXED: curve tracers and Output Impedance
- FW: [SI-LIST] : How to identify SSO groups?
- FW: [SI-LIST] : IBIS Model Verification (correction)
- FW: [SI-LIST] : Output Impedance
- FW: reactance of 0805 and smaller SMT resistors
- FW: SI engineers wanted - address correction
- Fw: Spice models???
- FWD from si-admin: Schottky Diode terminator SIP packages
- Fwd: [SI-LIST] : PCB design techniques for EMC control
- FWD: ASIC DESIGNER: case temperture OR ambient temperture...?
- FWD: Impedance Software
- Ground bounce
- Ground Bounce?
- Ground Plane Info
- Guard banding
- guard traces.
- guide line of PCB placement to reduce EMI/SI problem
- Happy Engineers Week!!
- Hello! Favorite pubs?
- Help
- Help with decoupling cap inductance
- Help/cross-talk guidelines
- HF SCSI connectors
- HFSS/Eminence User Group/Mail List Info
- hiring
- How to do correlation with two extra Rising/Falling waveforms?
- I/O BUFFER MODELING POSITION
- I/O Model opening at Intel
- ibis 3.0
- IBIS connector models
- IBIS Models or full spice netlist...?
- IEEE Workshop "Signal Propagation on Interconnects"
- IMAPS Orange Chapter April Meeting L.A. Area
- IMAPS Orange Chapter March meeting L.A. Area
- impedance across ground plane
- Impedance Software
- Inductance calculation
- Inter-Symbol Interference
- intersymbol Interference
- Is feedback really EVIL?
- ISO Bob Canright
- Job Opening at Apple
- Job Opening: Beaverton, OR
- JOB POSTING
- Jobs forum
- Joint Technical Societies, Nepcon West, L.A. Area
- Junior Hardware Design Engineer
- L/R response time
- lab electrical requirements
- limit of method of moments
- Limits in MoM calculations
- Line Parameters of twisted cables
- Line Parameters of Twisted Cables ?
- Looking for Signal Integrity Engineer
- math sw for Unix???
- MCMC '96 Advance Program
- measuring CMOS Cin with HP4275A
- measuring CMOS Cin with HP4275A - IPA510
- MEASURING POWER GROUND IMPEDANCE
- Message for SI List
- Message from mail server
- microwave radiation due to network analyzers
- Minimum or Maximum package for SI Worst Case simulation?
- Modeling - Fast Tr
- Modeling for packages (Electrical and thermal).
- Models for SCSI Ultra
- Module Hardware Design Engineer positions
- More on Eye Patterns
- More on Ground Planes
- more questions about buried PCB
- more questions about buried PCB capacitors
- MOTIVE Models
- NEC-LIST: test data?
- Need free 2D mesh Generation Software
- need help for networking loop back, Thanks
- need help for networking loop back, Thanks
- Need info on BGA packages
- need some info.....
- Networking loop back -- Please use my email address instead of replying button
- New shareware Visual IBIS development tool for Windows
- New t-line model in Hspice
- New version of Visual IBIS Editor V0.96
- Open position
- Package charcterization SW, S-I needs etc...
- Packaging Short Course flyer
- Partial Inductance
- Partial Inductance - NOT
- participation on the SI group
- PBGA packaging
- pc board AC noisemap standards
- PCB burried capacitance
- PCB SI simulation tools
- PCB Top Gun Showdown!
- pkg elect char job op
- Please add me to your mailing list.
- Position Available
- Position Open
- Position wanted
- Positions available
- Post articles to si-list NOT si-admin
- Power/ground connections/bypassing on ICs
- Program: 1996 Wireless Communications Conference
- Propagation velocity / discontinuous reference plane
- PSI Connector impedances
- Public SI Seminar
- Pullup resistors on 3-state buses
- Q: SI Course Inputs
- QUAD Model & Device capacitance
- R: [SI-LIST] : Serpentine traces
- R: need help for networking loop back, Thanks
- Radiation Losses of Transmission Lines
- RE : [SI-LIST] : IBIS Modeling
- Re : [SI-LIST] : Modeling Package parasitics
- RE : [SI-LIST] : Need your comments in selection of SI simula
- RE : [SI-LIST] : RE: Models & EDA Vendors
- RE : [SI-LIST] : RE: TDR modeling
- Re : Impedance Software
- RE : RE : [SI-LIST] : RE: Models & EDA Vendors
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter
- RE: 3.3V/5V planes
- RE: [SI-LIST] : 3.3V Design
- RE: [SI-LIST] : 5v and 3.3v
- RE: [SI-LIST] : 66 MHz AGP Clock Signal
- RE: [SI-LIST] : A timing question in high speed bus
- RE: [SI-LIST] : A/D and D/A Converters PWR/GND Connection
- RE: [SI-LIST] : AGP Buffer strengths
- RE: [SI-LIST] : AGP impedance compensated drivers?
- RE: [SI-LIST] : Ansoft 2D extractor question
- RE: [SI-LIST] : Backplane connectors for Fibre Channel
- RE: [SI-LIST] : bga
- RE: [SI-LIST] : Bus bar current carrying capability
- RE: [SI-LIST] : bypass cap question (long, simple)
- RE: [SI-LIST] : Cable skew
- RE: [SI-LIST] : Calculating Trace Inductance
- RE: [SI-LIST] : Clock tree
- RE: [SI-LIST] : Complex Planes
- RE: [SI-LIST] : Conducted EMC Testing of PLL jitter
- RE: [SI-LIST] : Convert an IBIS model to SPICE Model.
- RE: [SI-LIST] : Cross section geometry for the previous post
- RE: [SI-LIST] : curve tracers and Output Impedance
- RE: [SI-LIST] : Decoupling capacitor selection & placemen
- RE: [SI-LIST] : Decoupling:routing
- RE: [SI-LIST] : Design Note on Right Angle Bends
- RE: [SI-LIST] : Dieletric Constant Polyimide
- RE: [SI-LIST] : Differential impedance
- RE: [SI-LIST] : Differential Signals
- RE: [SI-LIST] : Diode Termination of Transmission Lines
- RE: [SI-LIST] : Diodes, EMC, ESD Protection networks
- RE: [SI-LIST] : Does IBIS describe output transition whic
- RE: [SI-LIST] : Does solder mask reduce trace impedance ?
- RE: [SI-LIST] : Driver Strength
- RE: [SI-LIST] : Dual Stripline impedance
- RE: [SI-LIST] : Earth Ground
- RE: [SI-LIST] : Effective Dielectric
- RE: [SI-LIST] : EMI
- RE: [SI-LIST] : Excessive clock overshoot
- RE: [SI-LIST] : field solver for differential pairs
- RE: [SI-LIST] : Focusing on Parasitic Parameters
- RE: [SI-LIST] : FW: signal isolation, RF board
- RE: [SI-LIST] : GND plane heat dissipation
- RE: [SI-LIST] : Guard banding
- RE: [SI-LIST] : HF SCSI connectors
- RE: [SI-LIST] : High Permittivity Board Level Decoupling and rela
- RE: [SI-LIST] : High Permittivity Board Level Decoupling and related issues
- RE: [SI-LIST] : High Speed Queries
- RE: [SI-LIST] : How to construct guard bands in Ansoft 2D
- RE: [SI-LIST] : How to identify SSO
- RE: [SI-LIST] : How to measure MOS capacitance
- RE: [SI-LIST] : IBIS Model Verification
- RE: [SI-LIST] : IBIS Modeling
- RE: [SI-LIST] : IC input impedance
- RE: [SI-LIST] : Inductance vs. frequency
- RE: [SI-LIST] : internal layer routing and EMI issues
- RE: [SI-LIST] : low-cost 2-D field solver
- RE: [SI-LIST] : measuring CMOS Cin with HP4275A
- RE: [SI-LIST] : Measuring Ground Noise
- RE: [SI-LIST] : Measuring PLL jitter
- RE: [SI-LIST] : MECL information
- RE: [SI-LIST] : Modeling Package parasitics
- RE: [SI-LIST] : mpc68360 Motorola IBIS models
- RE: [SI-LIST] : New VME Backplane -- Star Layout
- RE: [SI-LIST] : No subject given
- RE: [SI-LIST] : Other materials for GHz application
- RE: [SI-LIST] : Output Driver Impedance Variation?
- RE: [SI-LIST] : Output driver versus internal logic switching noise
- RE: [SI-LIST] : Output Impedance
- RE: [SI-LIST] : Overshoot/Undershoot
- RE: [SI-LIST] : Overshoot/Undershoot:
- RE: [SI-LIST] : PCB Pwr Planes
- RE: [SI-LIST] : PCI Slew Rate Test Load
- RE: [SI-LIST] : Preferred PWB impedances
- RE: [SI-LIST] : Propagation velocity / discontinuous reference pl
- RE: [SI-LIST] : RC terminations on multidrop busses
- RE: [SI-LIST] : RE: RC terminations on multidrop busses
- RE: [SI-LIST] : Regular Full-time Technical Positions
- RE: [SI-LIST] : RF experience VS SI issues
- RE: [SI-LIST] : Schottky diode termination
- RE: [SI-LIST] : Selection of Optimum Termination
- RE: [SI-LIST] : Signal integrity simulation tool - your opinion a
- RE: [SI-LIST] : Single-ended SCSI vs. di
- RE: [SI-LIST] : skin effect and transmission line simulators
- RE: [SI-LIST] : Skin effect Modeling and Verification
- RE: [SI-LIST] : Slew rate
- RE: [SI-LIST] : Some issues about fineline BGA ..
- RE: [SI-LIST] : SPICE for SI analysis
- RE: [SI-LIST] : SPICE or IBIS SI models
- RE: [SI-LIST] : SSO : How to identify SSO groups?
- RE: [SI-LIST] : SSO in ASICs
- RE: [SI-LIST] : SSO noise: Through current vs. Discharge current
- RE: [SI-LIST] : stackup question
- RE: [SI-LIST] : Standard Component Data Sheet again
- RE: [SI-LIST] : TDR Analysis: Layer Peeling Algorithm using Matlab
- RE: [SI-LIST] : TDR Measurements
- RE: [SI-LIST] : Terminations scheme for bi-directional bus
- RE: [SI-LIST] : Text Book in SI
- RE: [SI-LIST] : timing design tool
- RE: [SI-LIST] : To overshoot or undershoot: ( to diode or not to
- RE: [SI-LIST] : To overshoot or undershoot: ( to diode or not to diode)
- RE: [SI-LIST] : Trace impedance
- RE: [SI-LIST] : Trace impedance measurement for dual stripline
- RE: [SI-LIST] : Transmission Line Analysis Software
- RE: [SI-LIST] : Transmission Line Conductors
- RE: [SI-LIST] : Transmission line model in Pspice
- RE: [SI-LIST] : Transmission Line Theory
- RE: [SI-LIST] : viewing HSPICE results without awaves
- RE: [SI-LIST] : Worst case VI curve for PCI spec a reality?
- RE: continously variable delay line avail?
- RE: Differential clock
- RE: FCT806 Clock Driver
- RE: Help/cross-talk guidelines
- RE: Inter-Symbol Interference
- RE: Line Parameters of Twisted Cables ?
- RE: Modeling - Fast Tr
- RE: Partial Inductance
- RE: Partial Inductance (correction)
- RE: Power/ground connections/bypassing on ICs
- RE: RE : [SI-LIST] : RE: Models & EDA Vendors
- RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & pl
- RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & plac
- RE: Re[2]: [SI-LIST] : power supply filtering and bypassing
- RE: Re[2]: [SI-LIST] : USB & LVDS Differential signals routing
- RE: resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types
- RE: S-Parameter to SPICE Model Converter
- RE: Separate +5V Plane
- RE: Shielding
- RE: Twisted pair cables
- RE: Vcc power planes
- RE: Xtalk/Zo tools
- Re[2]: [SI-LIST] : Controlled impedance in Flex Circuit
- Re[2]: [SI-LIST] : Convert an IBIS model to SPICE Model.
- Re[2]: [SI-LIST] : Decoupling capacitor selection & plac
- Re[2]: [SI-LIST] : Decoupling capacitor selection & placemen
- Re[2]: [SI-LIST] : Does solder mask reduce trace impedance ?
- Re[2]: [SI-LIST] : How to identify SSO
- Re[2]: [SI-LIST] : Modeling Package parasitics
- Re[2]: [SI-LIST] : Output Impedance
- Re[2]: [SI-LIST] : power supply filtering and bypassing
- Re[2]: [SI-LIST] : Power Supply Noise Filters
- Re[2]: [SI-LIST] : USB & LVDS Differential signals routing
- Re[2]: impedance across ground plane
- Re[2]: Wanted...PCI bus 3V driver/receiver models
- Re[2]: Xtalk/Zo tools
- Re[3]: impedance across ground plane
- Re[4]: [SI-LIST] : Decoupling capacitor selection & plac
- Re[4]: impedance across ground plane
- Re[n]: Wanted...PCI bus 3V driver/receiver models
- reactance of 0805 and smaller SMT resistors
- reactance of 0805 and smaller SMT resistors? preferred suppliers?
- Relative Permeability and Resistivity of Eutectic Solder Ball
- resend the question. (The CGround plane on top layer?
- resend the question. (The Criteria of overshoot, undershoot, RingBack for different logic types
- resend the question. please answer to my fully E-mail address
- Resume
- S-Parameter to SPICE Model Converter
- S-parameters and non-linear devices
- s2ibis questions
- Schottky Diode terminator SIP packages
- Separate +5V Plane
- shield layer connection
- Shielding
- Shielding/ Guardbanding
- shields
- Short Course: High Speed VLSI Interconnecti
- SI Engineering Position
- SI engineers wanted
- SI job opportunity at Intel's DuPont, Washington facitlity!
- SI job opportunity in Intel Santa Clara
- SI Mailing List
- SI positions available at Compaq
- SI Software Now Available!
- SI- Termination Comment
- SI- Termination Comments Wa
- SI-LIST - Self and mutual inductance
- si-list access down until tommorrow (8-29-96)
- SI-LIST archives (was RE: [SI-LIST] : admin test message (ignore
- si-list archives now available on the world wide web !!!
- si-list has returned to operation
- si-list is alive and well (really)
- si-list mail list back on the net.
- SI-LIST now Automated
- si-list RE: 3.3V/5V planes
- SI-Termination Comments
- Signal Integrity advertisement
- Signal Integrity Applications Engineer
- Signal integrity contract position
- SIGNAL INTEGRITY ENG. OPENING
- Signal Integrity Engineering Position Available at Sun
- Signal Integrity Job:Austin,Texas-Hardware Design
- Signal integrity mail list
- Signal integrity opening
- Signal Integrity position available
- Signal Integrity Position Open at Sun Microsystems
- Signal Integrity Positions Open at Sun Microsystems
- Signal Integrity-Senior Hardware Desing Engineer
- Signaling Technologies
- Silicon Circuit Design for High Speed
- Silicon Circuit Design for High Speed and Low Power
- Simultaneous Switching
- Simultaneous Switching and differential buffer skew
- Skew, Skew, Differential Skew
- source for IEEE and JEDEC docs
- SPICE model for PCI driver
- Spice to IBIS
- split plane/micro-island
- subscribe to si-list
- Survey of Comp. Electromagnetics Professionals
- temporary si-list outage
- test - please ignore
- Test message . . ignore and delete
- The Criteria of overshoot, undershoot, RingBack for
- The Criteria of overshoot, undershoot, RingBack for different logic types
- Thermal Relief Design
- Trace impedance
- traces as antennas
- Transmission Line Conductors
- transmission line text
- Twisted pair cables
- TX-Austin-Hardware Design Engineer
- Unsubscribe from reflector
- Vcc power planes
- Vertical Transmission Line ...
- via clearance question
- Vias and decoupling (was Re[x]: impedance across ground plane)
- vias in ECL @ >1Ghz
- Viewlogic's XTK
- Wanted...PCI bus 3V driver/receiver models
- well done
- whadya know...
- What a disappointment...
- What is SSTL?
- What works?
- Who runs NEC under UNIX?
- Xtalk/Zo tools
- Zeelan Technology
Last message date: Sun 20 Jun 1999 - 03:56:60 PST
Archived on: Fri Mar 05 1999 - 14:11:27 PST
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