Re: [SI-LIST] : Down-bond in chip packaging

D. C. Sessions ([email protected])
Mon, 09 Feb 1998 09:39:45 -0700

Yehuda D. Yizraeli wrote:

> I am inveswtigating the various options of using the down bonds
> for our design. naturaly, one would like to connect all the VSS to the
> down-bond plate. However, the periphery supply, which makes the most
> noise, can then inject noise into the core logic, especialy to the PLL
> circuitry through the substrate (influencing input buffers' trip-point
> as well). So, my conclusion is to conect core and other non periphery
> VSS to the down-bond plate (paddle) and the periphery should be directly
> connected to the packages' pins.
> Do u agree with the analysis, can u point me to some areticles
> and/or literture on the subject..?

Our standard practice is just the opposite. Core current is
generally balanced so onchip bypassing takes care of the worst
of the high-frequency components, while most I/O types are
unbalanced and heavily dependent on supply inductance. We
run the I/O ring VSS and VDD supplies to the package rails
and supply core through either signal or secondary supply
balls. Either way, PLL supplies are as completely isolated
as possible, with no connection to either core or I/O supplies
short of the PWB planes.

D. C. Sessions
[email protected]