[SI-LIST] : Placement of series termination

Howard Johnson (howiej@sigcon.com)
Sun, 11 Jan 1998 20:51:35 -0800

I recently became interested in finding a simple expression
for the effectiveness of a series termination, as a function
of placement. We all know that a series termination is=20
supposed to be located "near" the driver, but what exactly
is the relation of location to performance?

This is a problem that can be handily solved by simulation
means, however, I am interested in finding a good general-
purpose approximation, one that can be done on a hand calculator,
or plotted on graph paper. That's the kind of solution that
will see wide application in the general community of
digital engineers. If there's one thing I've learned in all
my teaching experience, it's that most digital engineers
still don't have access to a simulator.

If anyone has any ideas, or comments about the method=20
described below, please drop me a line--I'm always ready to
discuss new ideas.

Best regards,
Dr. Howard Johnson

(**The following material may appear as part of an=20
upcoming editorial column for a national magazine. I'll
attribute your comments if they make it into publication**)

Assume your driver is connected to a series termination
resistor by a short stub of PCB trace.
The connection stub, because it is shorted at one end (to
the low-impedance driver), acts like a little inductor
LSTUB. The stub inductance acts in series with the
termination resistor, adding to the impedance of the
termination. If you add the impedance of the stub,
(j2(pi)f)LSTUB , to the resistor value, RT , you get a
reasonable model for the combined termination impedance.
Laplace transform theory tells us that any step waveform
hitting this type of termination impedance will generate a
short reflected pulse. The pulse amplitude will be
approximately (1/2)(LSTUB/Z0)(1/TR), where Z0 is the
transmission line impedance and TR is the 10-90% risetime of
the step waveform. This expression computes the amplitude of
the reflected pulse as a fraction of the input step height.
That=92s the theory, except for these embellishments:
1. The stub inductance may be calculated as LSTUB =3D DLY*Z1,
where DLY is the delay of the stub in seconds and Z1 is the
stub impedance.
2. Add to the stub inductance the parasitic series
inductance of the driver package, LPACKAGE.
3. Add a term to account for the mismatch between the line
impedance, Z0, and the total terminating resistance, which
equals RT plus the driver output impedance, RDRV .
With those modifications, here is the final version of the
reflection estimator:

Refl. =3D (1/2)((LPACKAGE + DLY*Z1)/Z0)(1/TR)
+ |(RT + RDRV =96 Z0)/(RT + RDRV + Z0)|

Example: BGA package, LPACKAGE =3D 6000 pH. The series
terminator is located 1/2 inch (microstrip trace) from the
driver package, so LSTUB =3D (1/2)(145 pH/in)(70 ) =3D 5100 pH.
Total inductance, LTOTAL =3D LPACKAGE + LSTUB =3D 11100 nH.
The driver impedance varies from 0 to 10 , and there is a
65-ohm resistor in series with the driver. The total
reflected fraction, for a 1000 pS rising edge, will be:
Refl. =3D =BD[(11100/70) / 1000 ]
+ |(65+10-70)/(65+10+70)| =3D 0.114
After the first round-trip on the line, a signal of
size 0.114 will still persist. After the second round-
trip, the residual refelctions will be down to (0.114)2,
or about 1.2%.

* * * END * * *=20

Dr. Howard Johnson, Signal Consulting, Inc.=20
16541 Redmond Way, Suite 264, Redmond, WA 98052 USA
tel 425.556.0800 // fax 425.881.6149 // email howiej@sigcon.com