design is to be a Synchronous clock one"? If so, the flight time falls =
the equation and only the skews need to be worried about. (Source
means that both the data and the clock [strobe] are sent by the driver
the receiver and they travel down the distance side by side. So it =
matter how long it takes for the signal to get there as long as they =
I have to design a backplane bus with about 100M Hz clock and the
distance wanted as long as it can, using GTL . The design is to be a
clock one . The component we want to use as transceiver is =
specification said that it can function up to 200 Mhz clock frequency .
But I have a puzzle about the high speed bus's timing:
You know, the formula: "TFLT_MAX <=3DClock Period - TCO_MAX - TSU_MIN
CLKJITTER"(TFLT_MAX is the largest flight time a network will =
all variation of conditions,TCO_MAX is the maximum colok to output=20
specification, TSU_MIN is the minimum required time specified to setup
the clock,CLKJITTER is the maximum clock edge to edge variation,CLKSKEW =
maximum variation between components receiving the same clock edge.) =
bus,the Clock Period is 10ns, and for TI's SN74GTL16622,TCO_MAX is =
(maximum of TPLH from CLKAB to B is 6.1ns),TSU_MIN is 2.6ns. In some =
as Intel's Pentium II Processor GTL+ Guidelines, they give the CLKSKEW =
CLKJITTER is about 0.4ns and 0.25ns. Then the TFLT_MAX is about only =
<?/smaller> It's clear that the flight time is not enough , for =
NESA's paper "An Innovative Distributed Termination Scheme for GTL =
Designs", they used the GTL+ to implement 100MHz bus , the delay of=A0 =
distance is 1.62ns=A0 (this delay time is not the flight time, it's =
it.), and my design have to be much longer than 9 inches .=A0 So I am =
is the calculation wrong, or others?
<?/smaller>=A0 How can I settle the timing question ?
(By the way, the maximum of TPLH from CLKAB to B is 6.1ns , how can it =
200MHz clock frequency ?)
Thank you .
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