design is to be a Synchronous clock one"? If so, the flight time falls =
out
from
the equation and only the skews need to be worried about. (Source
synchronous=20
means that both the data and the clock [strobe] are sent by the driver
device to
the receiver and they travel down the distance side by side. So it =
doesn't=20
matter how long it takes for the signal to get there as long as they =
get
there=20
together).
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D
=3D=3D=3D
Dear list,
I have to design a backplane bus with about 100M Hz clock and the
transmission=20
distance wanted as long as it can, using GTL . The design is to be a
Synchronous
clock one . The component we want to use as transceiver is =
SN74GTL16622, the
specification said that it can function up to 200 Mhz clock frequency .
But I have a puzzle about the high speed bus's timing:
You know, the formula: "TFLT_MAX <=3DClock Period - TCO_MAX - TSU_MIN
-CLKSKEW-=20
CLKJITTER"(TFLT_MAX is the largest flight time a network will =
experience
under=20
all variation of conditions,TCO_MAX is the maximum colok to output=20
specification, TSU_MIN is the minimum required time specified to setup
before=20
the clock,CLKJITTER is the maximum clock edge to edge variation,CLKSKEW =
is
the=20
maximum variation between components receiving the same clock edge.) =
For
100MHz=20
bus,the Clock Period is 10ns, and for TI's SN74GTL16622,TCO_MAX is =
6.1ns=20
(maximum of TPLH from CLKAB to B is 6.1ns),TSU_MIN is 2.6ns. In some =
papers
such
as Intel's Pentium II Processor GTL+ Guidelines, they give the CLKSKEW =
and=20
CLKJITTER is about 0.4ns and 0.25ns. Then the TFLT_MAX is about only =
0.65ns.
<?/smaller> It's clear that the flight time is not enough , for =
example, in
the=20
NESA's paper "An Innovative Distributed Termination Scheme for GTL =
Backplane
Bus
Designs", they used the GTL+ to implement 100MHz bus , the delay of=A0 =
9
inches=20
distance is 1.62ns=A0 (this delay time is not the flight time, it's =
just a
part of
it.), and my design have to be much longer than 9 inches .=A0 So I am =
puzzled=A0
,=20
is the calculation wrong, or others?
<?/smaller>=A0 How can I settle the timing question ?
(By the way, the maximum of TPLH from CLKAB to B is 6.1ns , how can it =
work
on=20
200MHz clock frequency ?)
=A0
Thank you .
**** To unsubscribe from si-list: send e-mail to ma[email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****