This is not really true. The V/T curve in the IBIS model definition does not
give any information about the PMO/CMOS overlapped current.
The V/T describes the behavior of the buffer output versus frequency but does
not give any information on the current passing internaly through the output
To know the value of the through current it is necessary to know the "Ron"
variation of the two transistors during the transition periode. The value of
this current depends upon the equivalent impedance of the two transistors,
impedance which is connected between Vdd and Vss power supply.
Jean Claude Perrin
From: Vinu Arumugham <email@example.com>, on 5/12/98 10:56 PM:
To: John Lin - TAO <LinJohn@digital.com>
Cc: "'IBIS_USER'" <firstname.lastname@example.org>, "'SI_LIST'" <si-list@silab.Eng.Sun.COM>
IBIS models also have V/T curves. These should cover overlapped
John Lin - TAO wrote:
> Dear IBIS fans/SI Experts,
> As I know for a CMOS device, during output transition, both PMOS and
> NMOS will turn on in a short period of time. I wonder if an IBIS model
> describes this behavior. If yes then how it does. Will the behavior
> affect the accuracy of simulation with IBIS model?
> Based on what I know the V-I curve for PULL UP or DOWN is obtained by
> turning one MOS off and then swift the V-fixture to get Current reading.
> It seems to me that the V_I curve doesn't contain the information to
> describe the transition, both PMOS and NMOS turned on.
> Any comment?
> CAE Engineer of EDA Department
> Digital Equipment Corp. Taiwan Branch
> Email: Linjohn@mail.dec.com <mailto:Linjohn@mail.dec.com>
> TEL: 1-886-3-3900000 ext. 2152
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