[SI-LIST] : Decoupling capacitor selection & placement

Andrew Phillips ([email protected])
Wed, 29 Oct 1997 14:00:28 +0800

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Please forgive me if my questions have been asked a million times before

When using decoupling capacitors to provide a low-impedance path between
power and ground it appears to be well-established that we must do the

- from device Vcc pin we drop a via to Vcc plane with as short a
connection as possible (to minimize lead inductance). Same for device
Gnd pin.
- from capacitor pads we also drop vias to Vcc and Gnd planes with very
short connections.

What is the ruling for how close the capacitor needs to be to the device
Vcc and Gnd pins?

For a device such as a microprocessor with multiple Vcc and Gnd pins,
how do we determine how many capacitors will be required?

Many references suggest that using 1 x 0.1 uF cap per Vcc-Gnd pair is a
good rule-of-thumb - how is this value determined, and are there
situations when it is invalid?

Thanks for any help,

Andrew Phillips
Cooperative Research Centre for Broadband Telecommunications &
Perth, Western Australia

p.s. anyone interested in the Texas Instruments TMS320C6x DSP, please
check out my info site:


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