Re: [SI-LIST] : Some issues about fineline BGA ..

Mike Degerstrom ([email protected])
Fri, 20 Nov 1998 08:31:23 -0600


On Nov 19, 6:04pm, Andrew Phillips wrote:
> Subject: [SI-LIST] : Some issues about fineline BGA ..
> Hello,
> Having a look at new fineline BGA packages and the task of breaking out
> their signals onto a PCB - it appears that unless expensive blind vias
> are used, it is necessary to increase the number of signal layers
> considerably. Altera recommends 9 signal layers unless you can fit 2
> traces between vias (which needs 5 mil traces and very small vias -
> cheaper to add layers). Any recommendations on board stack-ups for these
> requirements?

We will be soon facing a similar problem. What is your BGA package
size? What are your pin pitches? Is it a full array of pins, or
are there some sparse or missing rows? Maybe there is a web site
showing this part that you could point me to?

> Also - I believe - that in normal situations, as long as decoupling caps
> and supply pins have their connections to PWR/GND planes made with very
> short trace lengths, it is not very important to get the cap really
> close to the supply pins - the inductance of the power planes is so low
> it doesn't matter much - better to make routing life easier by shifting
> them away a bit if needed.
> For the fineline BGA packages they seem to have lots of VCC, GND pins
> clustered in the centre of the chip (well at least the Altera FLEX10KE
> devices do). All decoupling caps will have to be placed around the
> outside of the device. Breaking out the device signals with through-hole
> vias is much cheaper - but this leaves the power planes looking like
> Swiss cheese.
> Has anyone looked at this and worked out how much it affects plane
> inductance? How critical is the placement of decoupling caps with these
> packages??

I always try to make the ground/power planes as solid right around
the package, then add caps a little further away from the package. I
think that Larry Smith, et. al., have posted here several times to
that effect. Also it doesn't do too much good to put caps close
together. For example, if you were to place eight caps, I wouldn't
put them in pairs at each corner but spread them uniformly around
the package.

I once saw where someone used a mesh array of routes to form
a sparse plane beneath a PGA. Once powered up, the outputs
on this device just oscillated instead of acting like a digital

One more thought, it would be hard to specify a board stack-up
without knowing what your chip power and ground requirements are.
Also, it is important to know what kind(s) of I/O will need
to be supported. For example, if you are using full differential
I/O, then the Power/GND requirements are much more relaxed over
non-differential I/O.


Mike Degerstrom         Email:    [email protected]	
Mayo Clinic 
200 1st Street SW 
Gugg. Bldg. RM 1042A                 Phone:    (507) 284-3292
Rochester, MN 55905                    FAX:    (507) 284-9171

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