Hi Jeff,
Since this is a CE* signal to a memory device, I'm going to assume
the driver is some sort of decoding logic, and the receiver,
obviously, is the memory device. Your net probably consists of
a few inches of track connecting driver to receiver, and nothing
else. The track will have a characteristic impedance Zo, which
is very close to being lossless, and therefore a real number. A
reasonable guess for Zo might be 50 to 60 Ohms??
The driver has an output impedance Zd, which is actually non-linear
and best modeled with a current-voltage relationship. But, for
simplicity, assume real, linear values of 30 Ohms for both the low
and high states.
As your driver transitions from one state to the other, a portion
of the transition is launched onto the track, and a portion
dropped across it's output impedance. The portion launched can be
approximated using the voltage divider formula:
Vl = Zo*Vs/(Zo + Zd) = (2/3)*Vs (for example values above)
Where Vl = voltage launched onto the track, and
Vs = the source voltage transition,
If the delay encountered between driver and receiver is > 50% of
the source risetime (approximately, many will argue for a different
percentage), there will be a noticeable over/undershoot on the signal
transition at the receiver. This is due to reflections resulting from
the mismatch between the line impedance Zo, and the receiver impedance,
Zl. The reflection coefficient p, is given by:
p = (Zl - Zo)/(Zl + Zo)
Your memory device will appear slightly capacative, but if we approximate
Zl as an open circuit, we get:
p = 1.
Thus, 100% of the signal arriving at the receiver will be reflected back
toward the driver. The voltage at the receiver Vr, is the sum of the incident
and reflected signals (waves):
Vr = Vincident + Vreflected
If Vincident = Vl (launched voltage), and p = 1, we get:
Vr = (2/3)*Vs + (2/3)*Vs = (4/3)*Vs
If the source signal swing is rail-to-rail, the above predicts receiver
signal over/undershoot of 1/3 the supply voltage.
If the track delay is a smaller part of the source risetime, lesser amounts of
over/undershoot will be experienced. In fact, if delay is < 25% of the source
risetime, it is unlikely any overshoot problems will occur.
Also, if the driver falltime is shorter than it's risetime, and/or its output
impedance is smaller in the low state, you will experience greater undershoot,
and longer sustained ringing on the high-to-low transitions.
BTW, after all this, the fix for your situation is to match the driver output
impedance to the line. This normally entails placing a series resistor Rs, at
the driver output such that:
Zo = Zd + Rs.
This will cause the launched signal to be 50% of the driver's transition. The
signal at the receiver will then be 100% of the driver's transition. This is
a bit idealized, but the point is valid. In the real world, you might choose
a series resistor which allows 55% to 60% of the source transition to be
launched. Many times you must compromise because of driver asymmetry, launching
a greater portion of the high-to-low transition, or visa versa. Also, I have
neither accounted for the capacitive nature of the receiver's impedance, nor any
discontinuities caused by routing diversity. And finally, a little overshoot is
not harmful. Fear not a few hundred millivolts. What must be avoided is overshoot
which causes repeated hard turn on of protective clamp devices, or substrate currents.
(Some of the semiconductor types which inhabit this list can better tell you of
such harm).
Cheers,
Dennis
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