RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & pl

RICHARD_BRUSH@hp-santaclara-om3.om.hp.com
Thu, 6 Nov 97 13:00:06 -0800

Item Subject: RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & plac
Ravinder, Jim Peterson,

I have designed a number of high speed boards (both digital and mixed
analog/digital) using a GND and PWR plane separated by FR4 dielectric
of .004-.005". This is thin enough to give some decent capacitance but
does not require special or expensive fabrication. Depending on the
circuit complexity additional internal signal and GND layers may also
be required, but I do not place them between the GND and PWR planes. I
have not used this construction to eliminate bypass capacitors but
rather to provide local, very high frequency (essentially non
resonant) capacitance above the self resonant frequency of most SMT
bypass capacitors.

In addition to the high frequency PCB capacitance, any power supply
noise due to device switching (especially prevalent in high speed TTL
and CMOS ICs) tends to be confined to the inner adjacent surfaces of
the GND and PWR planes due to skin effect at high frequencies and thus
does not contaminate signals on other layers.

In addition I have found it highly effective in terms of reducing
noise and EMI to isolate the small PWR plane area surrounding clock
sources and buffers with a ferrite bead while providing very good
bypassing of such devices.

In most systems clocks are the major contributor to noise and EMI (as
seen on a spectrum analyzer) and it makes sense to minimize this noise
at the source where it is relatively easy to do so.

______________________________ Reply Separator _________________________________
Subject: RE: Re[2]: [SI-LIST] : Decoupling capacitor selection & pl
Author: Non-HP-jfpeterson (jfpeterson@space.honeywell.com) at hp-boise,shargw18
Date: 11/6/97 6:35 AM

Ravinder,
I am interested in your power plane capacitance analysis. Apparently
you've done some tests in this area. Empirical data is always good.
Could you give me the details of how you tested and what type of numbers
you got from your measurements.
I am considering straying from a dual stripline approach in my stackup
to put a +5 and gnd next to each other. The reason was to add some high
freq. capacitance to the board. Text books have stated that a pwr and
gnd plane separated by 10 mils of FR-4 have a capacitance of 100 pF/sq
inch. Does that match what you saw in your tests?
If not, I might reconsider my approach...
Thanks in advance for the info,
Jim Peterson
jfpeterson@space.honeywell.com

> ----------
> From: Ravinder Ajmani[SMTP:ajmani@us.ibm.com]
> Sent: Friday, October 31, 1997 11:50 AM
> To: si-list@silab.Eng.Sun.COM
> Subject: Re: Re[2]: [SI-LIST] : Decoupling capacitor selection &
> plac
>
> I have been studying the effects of increased power/ground capacitance
> on noise
> and EMI, and also to determine if I can use this option to reduce the
> number of
> capacitors on the board. I have used FR4 with thickness of 3 mils,
> and also
> Zycon material, which is 2 mils thick but is still FR4, and hence
> doesn't
> provide enough capacitance to make any significant difference. I have
> inquired
> with our raw card fabricators and none could provide me any details
> about high
> dielectric constant material.
> I will be interested in using the EmCap material in my experiment. I
> will
> appreciate if Todd can inform me who in California has the capability
> to
> fabricate boards with this material.
>
> Regards, Ravinder
> EMC & Signal Integrity Engineer
> PCB Development and Design Department
> Voice : (408) 256-7956 T/L : 276-7956 Fax : (408)
> 256-0550
> Email: ajmani@us.ibm.com
>
>
> owner-si-list@silab.Eng.Sun.COM
> 10/29/97 05:11 AM
> Please respond to owner-si-list@silab.Eng.Sun.COM @ internet
>
> To:
> cc: si-list@silab.Eng.Sun.COM @ internet
> Subject: Re[2]: [SI-LIST] : Decoupling capacitor selection & placemen
>
> How does everyone feel about power/ground distributed
> capacitance?
>
> Zycon originally developed ZBC2000 - a thin FR4 (.002")
> power/ground
> core with a capacitance of ~500pf/sq in (usually 2 cores are
> used) -
> as a decoupling capacitor replacement or adjunct.
>
> HADCO and Polyclad have developed EmCap - a 0.004" Ceramic / FR4
> epoxy
> power/ground core with 2750pf/sq in - as the next generation.
>
> I have been doing work to predict the ability of both these
> products
> to replace discrete capacitors in our customers boards and would
> like
> to hear some honest thoughts and feedback.
>
> FYI - I'm an EE working at HADCO. I work with the electrical
> issues in
> PWB - impedance, capacitance, layout, etc. - more or less in
> house SI.
>
> Thanks!
> Todd DeRego
>
>
>
>
>
>