Does anyone know of a paper or application note which gives
design rules for the sizing of ASIC I/O strength and Vdd/Vss
pin count, based on the notion of distributed, rather than lumped
When our ASIC designers estimate the number of Vdd/Vss pin pairs
that are needed for a particular design, they apply the foundry's
rules for SSO noise limitation.
The founder's rules are very sensible: stronger buffers with fast
edges mean more Vdd/Vss pairs. However, I'm not convinced by
the relationship with load capacitance i.e. that the greater the
capacitive load, the more Vdd/Vss pairs are needed, due to the
fact that the capacitive load is distributed.
Does a load at 20cm from the source really affect SSO noise?
I don't think so. But at 10cm? 5cm?
I would be more at ease with a rule which took into account the
impedance of the line being driven, rather than the total
capacitance. I believe that such a rule would lead to a
lower, and truer, estimation of the number of supply pins needed.
Thanks in advance,
-- John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr> Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09