One of my college physics profs taught us that it was very important to be able to estimate a value for any effect, quickly, even if it is just within an order of magnitude. After all, physics is all about quantitatively predicting the behavior of the real world. These are often called "back of the envelope estimates". My prof used to challenge us by asking if we were stranded on a desert island and all we had was a stick, some blank sand and what we could remember, calculate a value.
I encourage all fellow signal integrity engineers to develop this habit. Learn to estimate, even if its only very approximate, the magnitude of effects. This ability will give you great insight into what to worry about and what not to worry about. 2 minutes up front may provide days of relief. Of course, estimating should not be the basis of signing off a design. It should be used, however, as directions of where to place resources for further analysis. Like in any good pareto analysis, tackle the first order effects first.
So, here's my attempt to estimate the impact of a corner on signal integrity, if I were stranded on a desert island and I needed to come up with a value, fast.
First, I assume the influence of a corner is to add an extra amount of trace capacitance comparable to 1/2 a square- like a stub. Indeed, if you look at the TDR from a trace having a corner, it shows a dip, corresponding to a capacitive load (and has been pointed out, its a very small dip!)
I happen to remember that the capacitance per length of a 50 Ohm line made from a dielectric constant of 4 is about 3.5 pF/inch- this is independent of the actual dimensions, as long as it is 50 Ohms.
The length of this 1/2 a square of stub is L = 1/2 x w, where w is the line width of the trace. So, the capacitance of this corner stub is C = 3.5 pF/inch x 1/2 x w (w, of course, in inches) = 1.7 pF/inch x w.
If the trace width is 10 mils, for example, the capacitance of the corner would be about 17 fF.
What is the effect on a signal of a 17 fF load? You can always do a circuit simulation with SPICE to see the effect of a 17 fF load on your signal traces. Or, we can do a simple, quick estimate to evaluate under what condition 17 fF load might be important.
For a 50 Ohm system, the signal propagating down the line will be degraded with an additional rise time of 2.2 x 20fF x 50/2 Ohms ( the 2.2 gives the 10-90 rise time and I used 20 fF because its easier to calculate and its an approximation, after all, and the /2 comes from the fact that the T line is effectively in parallel to the C) = 1 psec additional delay. Sometimes, a 1 psec of additional delay is important, especially if there are a number of corners in the same trace.
The magnitude of the reflected signal will be a dip. Assuming the rise time of the signal is longer than the delay time, then the depth of the dip will be Vdip/ Vsource = 1 psec/t_rise. For a 100 psec rise time, you would see a 1% reflected noise pulse. For a 25 psec TDR trace, you would see a dip of about 40 milli Rho. This is very small, but measurable if you are careful.
Is a corner important in Si applications- its not the first thing I would worry about. I would worry about the control of the board impedance, connectors, packages, power and ground distribution inductance and cross talk first.
try this at home for your specific characteristic impedance, line width and rise time.
At 03:51 PM 7/10/98 -0400, Greg Edlund wrote:
>Well said. You could almost say the whole art and science of
>engineering is knowing when to worry about what. Anybody can be so
>conservative that their design will always work - only the product will
>never make it to market. The real trick is knowing how close to the
>cliff is safe enough, and that's where we have to fall back on our
>understanding of the fundamentals and ability to make first-order
>estimates. In today's world, this is no small feat.
>Greg Edlund, Principal Engineer
>Server Product Development
>Compaq Computer Corp.
>129 Parker St. PKO3-1/20C
>Maynard, MA 01754
>(978) 493-4157 voice
>(978) 493-0941 FAX
> Sent: Friday, July 10, 1998 2:47 PM
> To: si-list@silab.Eng.Sun.COM
> Subject: Re: [SI-LIST] : Design Note on Right Angle Bends
> I believe we're once again seeing a potential misapplication
> of rules of scale. That is, a rule like this might have
> value and accuracy in certain applications, but is easily
> applied to areas where it isn't true. For a long time
> people working with digital signals with transition times
> over 1 ns were told not to use right angle corners due to the
> impedance bump. In reality that bump isn't easily measured with
> 20 to 30 ps transition time TDRs for common PCB layups and
> trace widths. So, a true statement misapplied. Right angle
> corners do cause impedance bumps, just not anywhere near the
> scale of vias, parts packages, surface mount pad patterns for
> termination resistors, etc.
> In this case it may be perfectly true that for some
> the right angle PCB trace corners act as antennas and cause
> radiation. However, if we need to eliminate right angle corners,
> how about vias, part leads, routes on the silicon, and all the
> other right angle corners. Does make one wonder doesn't it?
> Like you, I've never seen any rigor applied to these statements.
> Perhaps someone on the list can enlighten us both. Not to if
> right angle corners *can* act as antennas, but as to the effects
> significance for what range of geometries, frequencies, etc.
> > From Mike.Mayer@heurikon.com Fri Jul 10 13:32:02 1998
> > Date: Fri, 10 Jul 1998 13:17:15 -0500 (CDT)
> > From: Mike Mayer <<Mike.Mayer@heurikon.com>
> > To: si-list@silab.Eng.Sun.COM
> > Subject: [SI-LIST] : Design Note on Right Angle Bends
> > I am puzzled by a design note on the Ultracad web site:
> > http://www.ultracad.com/tech.htm
> > It states that:
> > THE REASON YOU DON'T USE RIGHT ANGLE TURNS ON CIRCUIT
> > THAT RIGHT ANGLE CORNERS BEGIN TO LOOK LIKE ANTENNAS.
> > There are no references given or any further explanation. Can
> > explain what they mean?
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