[SI-LIST] : Modeling connector pin vias

RICHARD_BRUSH@hp-santaclara-om3.om.hp.com
Wed, 29 Oct 97 10:26:15 -0800

Item Subject: cc:Mail Text

I am interested in modeling vias for through-hole connector pins in a
multilayer controlled impedance board.

I have found that I get lower TDR impedances on bussed signal traces
routed to several connectors than for a simple test trace of the same
geometry. This is true even on a bare board with no connectors or
other components installed.

The lower impedance appears to be due to parasitic capacitance of the
feedthroughs and associated pads and PWR/GND planes. Signal rise times
in my application are about 1-1.5ns, so it seems reasonable to model
the vias as an excess lumped capacitance at the connector pin nodes.


My guess is that pin capacitance is a function of connector itself
(which the connector manufacturer may provide a model for), as well
PCB parameters such as thickness, number of layers (including PWR and
GND planes), pad size and clearance to plane layers.

Does anyone know of a calculation tool or formulas to get an
equivalent lumped via/pin capacitance I can use with a transmission
line simulator?

Also does anyone have experience with the technique of clearing a
rectangular region of metal in the PWR/GND layers around the connector
signal pins to reduce excess capacitance? In my application, which
uses differential signals, the increased impedance and loop area for
common mode GND currents should be less troublesome than for single
ended signals.