Re: [SI-LIST] : Modeling connector pin vias

Tat Hin Tan (Tat_Hin_Tan@ccm.ipn.intel.com)
Wed, 05 Nov 97 10:48:00 PST

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> Date: Fri, 31 Oct 97 08:30:00 PST
> From: Tat Hin Tan <Tat_Hin_Tan@ccm.ipn.intel.com>
> To: owner-si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Modeling connector pin vias
>
>
> Text item:
>
> I'm not advertising for Tektronix but if u r looking for a
> software tool to extract the parasitics for connector pin vias, I do
> suggest IPA510 from Tektronix. It has powerful processing capabilities:
> it can perform a deconvolution to remove the inherent ringing in the
> step generated by the TDR, takes into account multiple reflections and
> helps generate a lumped equivalent circuit model.
>
> rgrds,
> Tan Tat Hin
> Intel Penang
> ______________________________ Reply Separator
_________________________________
> Subject: [SI-LIST] : Modeling connector pin vias
> Author: owner-si-list@silab.Eng.Sun.COM at SMTPGATE
> Date: 10/29/97 10:26 AM
>
>
> Item Subject: cc:Mail Text
>
> I am interested in modeling vias for through-hole connector pins in a
> multilayer controlled impedance board.
>
> I have found that I get lower TDR impedances on bussed signal traces
> routed to several connectors than for a simple test trace of the same
> geometry. This is true even on a bare board with no connectors or
> other components installed.
>
> The lower impedance appears to be due to parasitic capacitance of the
> feedthroughs and associated pads and PWR/GND planes. Signal rise times
> in my application are about 1-1.5ns, so it seems reasonable to model
> the vias as an excess lumped capacitance at the connector pin nodes.
>
>
> My guess is that pin capacitance is a function of connector itself
> (which the connector manufacturer may provide a model for), as well
> PCB parameters such as thickness, number of layers (including PWR and
> GND planes), pad size and clearance to plane layers.
>
> Does anyone know of a calculation tool or formulas to get an
> equivalent lumped via/pin capacitance I can use with a transmission
> line simulator?
>
> Also does anyone have experience with the technique of clearing a
> rectangular region of metal in the PWR/GND layers around the connector
> signal pins to reduce excess capacitance? In my application, which
> uses differential signals, the increased impedance and loop area for
> common mode GND currents should be less troublesome than for single
> ended signals.
>
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> Subject: [SI-LIST] : Modeling connector pin vias
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To: Tat_Hin_Tan@ccm.ipn.intel.com
Subject: Re: [SI-LIST] : Modeling connector pin vias
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