Thank you for your response. Perhaps one conclusion implied by your
email is following:
It is simpler to quantify parasitic via capacitance than via
inductance.
As a QUAD user, I have experienced the above concept. QUAD models a
via as purely capacitive, thereby ignoring via's inductive effects.
However, in a high frequency simulation, such omission of parasitic via
inductance can compromise the simulation accuracy.
Regards,
Abe Riazi
email: ariazi@anigma.com
>----------
>From: Mike Jenkins[SMTP:jenkins@lsil.com]
>Sent: Friday, November 20, 1998 7:05 PM
>To: 'si-list@silab.eng.sun.com'
>Subject: Re: [SI-LIST] : Focusing on Parasitic Parameters
>
><<File: vcard.vcf>>
>Abe,
>
>Here's my two cents on the parasitics of signal vias. Capacitance
>can be pretty reasonably upper bounded by the capacitance of a
>coaxial structure (C = 2*pi*eps*d/ln(b/a)) where b is the diameter
>of the antipad in the ground and power planes and a is the diameter
>of the via "barrel" and d is the board thickness. For the example
>from Howard Johnson's book, 0.53 pF = 2*3.14*4.2*(8.854 pF/m)*
>(0.062"/39.37inch per meter)*ln(3.95). That is, the ratio of
>antipad-to-barrel diameter is in the neighborhood of 4. Practically,
>it's somewhat less, since the capacitance formula is pessimistic.
>
>The other thing this formula is good for is telling the difference
>between 30-mil vias and 10-mil signal vias. For the latter, the
>antipad-to-barrel ratio is much larger, so the capacitance is
>correspondingly smaller.
>
>Regarding inductance, I think it's fairly pointless to try to
>calculate this without knowing the return current path. (Weber
>said this, not me.)
>
>Regards,
>Mike
>--
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Mike Jenkins Phone: 408.433.7901 _____
> LSI Logic Corp, ms/G750 Fax: 408.433.2840 LSI|LOGIC| (R)
> 1525 McCarthy Blvd. mailto:Jenkins@LSIL.com | |
> Milpitas, CA 95035 http://www.lsilogic.com |_____|
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
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