Most of our investigations to date on the subject of of parasitic inductance
have been done on capacitors instead of resistors. We have found that
the mounted inductance of capacitors in bypass applications is very heavily
dependent on the geometry of the mounting pads, the via placement and substrate thickness and to a much lesser extent on the value and vendor of the part.
The physical size of the part primarily determines the inductance contributed
by the part itself.
The self inductance of an SMT part is only one partial inductance element
involved in the total loop inductance of a mounted part. We have begun to
talk in terms of "mounted inductance" when discussing the parasitics
involved with bypass capacitors, as the total effective loop inductance
of a mounted part depends on the area of the loop that the current must
3D modeling with Maxwell shows the mounted inductance for
0805 size parts with a pad separation of 100 mils to run from about
.4nH to .9nH as the via height (dielectric thickness) ranged from
8 to 20 mils. On a 12mil thick board varying the via spacing from
about 60 to 130 mils caused the mounted inductance to vary from about
.45nH to .9nH .
We are presently studying the effects of via placement and the
effects of multiple vias on the mounted inductance values.
As I mentioned, this work was done on capacitors in bypass
applications where it is necessary to connect to power distribution
planes some vertical distance away. I would expect to see similar trends
for SMT resistors used in a similar manner. For RF applications where
you are utilizing the resistor in bias networks, attenuator pads, etc.
one would need to adjust their assumptions in the calculation of