I/O BUFFER MODELING POSITION

Jonathan Dowling (jond@qdt.com)
Tue, 27 Aug 1996 09:59:41 -0700

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All,

Quad Design Technology (A Viewlogic Company) has an opening for a Senior I/O
Modeling Engineer. Basic job responsibilities are to create models for specific
XTK customer requests and to enhance/add to XTK libraries.

The candidate must have...

o Strong background in high speed PCB design issues
o BSEE/MSEE/PHDEE degree
o General knowledge of Transmission Line Analysis, Signal Quality Parameters, and
Electromagnetics.
o In depth knowledge of I/O Buffer Modeling, specifically behavioral (IBIS-like)
modeling for high speed digital logic.
o Candidate must be a self-starter and be able to work with little direct supervision.
o General knowledge of analog simulation (SPICE, HSPICE, PSPICE, etc.)
o General knowledge of Quad Design's XTK
o Knowledge of device physics for current signalling technologies.
o Knowledge of package characterization (electrical) with 3-D field solver
(XFX3D or other) and TDR // Network Analyzer measurement.
o Simple Board Layout with Mentor Graphics BoardStation, Cadence Allegro, or other
similar software.
o Knowledge of JTAG-Boundary Scan (IEEE 1149.1)
o HP-VEE, C, Perl, programming
o UNIX, Windows95, WinNT operating systems
o Familiarity with HP lab equipment (Oscilloscope, TDR, Power Supply, Pulse
Generator, Logic Analyzer, C-V meter, Semiconductor Parameter Analyzer, etc.)
o Must be able to understand and subsequently refine the model development process
flow.
o Good interpersonal communications skills.
o Willing to move to sunny Southern California.
o Comfortable working in a lab setting.

Please direct all inquiries to Jonathan Dowling by sending email to
jond@qdt.com or by FAXing your resume to (805)988-8259.

Jonathan Dowling
Quad Design

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