Re: [SI-LIST] : Decoupling capacitors

Ray Anderson ([email protected])
Wed, 12 Aug 1998 09:25:10 -0700 (PDT)

> >
> > The objective is to get the least amount of impedance (inductance)
> > between the power consumer (asic) and charge storage (capacitor).
> > That is usually accomplished by placing vias from the cap to the power
> > planes, and then vias from the power planes to the asic. Traces
> > make a lot of inductance. Manufacturing soldering rules generally

> Does it mean then that the capacitors can be placed freely around the chip
> to ease placement and routing and they don't have to be placed as close as
> possible to pwr or gnd pins?

At, what I like to call, SI frequencies (below the frequency of
the first board resonance) placement of decoupling capacitors is
relatively forgiving as compared to placement of decoupling capacitors
intended to provide a low impedance at EMI frequencies (at or above the
frequency of the first board resonance).

At "low" frequencies the spatial placement effect seen at
"high" frequencies is pretty much absent and the designer needs to
concern himself/herself with the decoupling capacitors providing a
low impedance current source to the chips attached to the power
distribution planes by means of a low impedance path. In this case "low
impedance" means having a low resistance and inductance path.

The power planes have an intrinsic resistance determined by
the metallization thickness as well as a frequency dependent resistance
known as skin effect. There is also a finite inductance associated with
the power planes that is about 0.13nH/square for boards with 4mil
plane separation or 0.065nH/square for 2 mil separation.

Unless you are dealing with very high currents or relatively long
current paths you may be able to ignore the resistive effect, however the
inductive effect is very real and the inductance is in series with the
current coming out of your current source (the decoupling capacitor)
going to your current consumer (the IC). The farther the decoupling
capacitor is from the chip, the more series inductance in the planes
will be present.

So for applications that will have low delta-I associated with
a chips power consumption needs, the L*dI/dT product will be low and you
can tolerate a fair amount of series inductance (distance to the
decoupling capacitor). In those cases where the L*dI/dT product is
not low you can experience circuit malfunction due to the voltage drop
developed across the inductance. The cure is to get your decoupling
capacitor closer to the IC .

Bear in mind that planar power distribution structures with
lots of mutual coupling between planes (closely spaced) will provide the
lowest inductance structure. If you use traces to connect your decoupling
capacitors to your IC's power pins you better keep them VERY close as the
inductance of the traces can be be many, many times the inductance associated
with a planar structure of the same lineal dimensions.


Ray Anderson
Sun Microsystems