Re: [SI-LIST] : another stack-up question

D. C. Sessions (dc.sessions@tempe.vlsi.com)
Fri, 01 May 1998 14:14:25 -0700

Paul Taddonio wrote:
>
> D. C. Sessions wrote:
> >
> > Andrew Phillips wrote:
> > >
> > > Hi,
> > >
> > > There was a recent discussion on this list regarding a stack-up proposal
> > > for a 10-layer board. Here's another one:
> > >
> > > signal
> > > GND
> > > signal
> > > signal
> > > PWR
> > > GND
> > > signal
> > > signal
> > > GND
> > > signal
> > >
> > > I'd be interested in any comments on the merits (or lack of) for this
> > > arrangment
> >
> > Return currents will see a different impedance on PWR vs GND, for one.
> > Worse, the returns on 7 & 8 will have to cross layers to get to PWR,
> > which should make for (1) much more noise, and (2) assymetrical edges
> > at the receiver.
> >
> > --
> > D. C. Sessions
> > dc.sessions@tempe.vlsi.com
>
> DC, your answer has left me a little bit confused.
> Let me see if I got this right:
>
> The different impedance of GND and PWR is due to many GNDs connected in
> parallel (presumably by vias) versus only one PWR plane.
>
> Isn't this alleviated by the PWR plane forming an integrated capacitor
> with the adjacent GND plane? (making the PWR plane nearly identical
> AC-wise to the GND plane)
>
> Why do you say that return currents have to get back to PWR?
>
> Since they are AC, they flow through the closest AC reference
> plane, be it PWR or GND. The only danger occurs if any
> signal crosses to another layer which has a different
> "closest AC reference plane".

TINSTAG -- There Is No Such Thing As Ground. Kirchoff's
Law is what's happening here. On a rising edge, the driver
creates a path between the Vdd node and a signal line. As the
line charges, some current is induced on both the Vdd and adjacent
planes, and eventually (via the receiver) in the Vdd and Vss
connections of the receiving device. Ultimately these currents
must get back to the driver's Vdd node.

About the best we can do is have about half of them on the Vdd
plane and half on Vss, but that at least gives symmetrical loop
impedances. If there are two Vss planes and no Vdd plane, the
rising edges will have higher loop impedances than the falling
edges and the signals will reflect this.

Also note that even in less-demanding systems where there isn't
a problem with the signals themselves, doubling the amount of
current that has to cross between planes isn't a good thing for
RFI purposes.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com