I think it is just to give both pullup and pulldown transistors a little
bit of loading to work against.
For most drivers it might not make much difference ... or maybe it does
... but it surely would if the driver uses something like an N-channel
pullup transistor (which turns off as Vout gets to within a volt or two
Many TTL devices had similar test loads, often two 500 ohms with the
upper one going to +7V, especially for testing 3-stateable devices. The
typical CMOS/TTL test load for normal outputs is a capacitor and a
resistor to ground. But that might bias things slightly in favor of
faster fall times. You could use a pulldown in one case and a pullup in
the other ... or just combine the two into one test load.