Re: Power/ground connections/bypassing on ICs

Michael Nagel (mina@force.de)
Mon, 28 Apr 1997 19:56:48 +0200

Andy,

One question and a lot of different answers, here's mine:

Decoupling for me is to stop the noise from an IC before it spreads all
over the board. You need a *good* groung plane for this and the right
bypass capacitor with a low-inductance layout. Bringing ground from
the plane is not what I would do, you possibly have a slight ground shift
depending on the consumption and additional inductance.


Try it like this:

+----------+
###| |###
vias | |
x x ###| |###
===== | |
x=###=x ###| GND |###
capacitor | | | |
=###===###| VCC |###
x=====x | |
x x ###| |###
+----------+
I.C.

Putting several vias in parallel decreases inductance and thus increases
the resonance frequency.

Decoupling only works below the self-resonance of capacitor+layout+IC leads.

A different approach to this subject you can find in the article of Prof.
Christian Dirks in the german magazine "Elektronik" 23/1996.

Regards,
Michael

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>From ingraham@wrksys.ENET.dec.com Mon Apr 28 18:10:57 1997
Date: Mon, 28 Apr 97 11:40:12 -0400
From: ingraham@wrksys.ENET.dec.com (Andy Ingraham)
To: si-list@silab.Eng.Sun.COM
Cc: INGRAHAM@US8RMC.bb.dec.com
Subject: Power/ground connections/bypassing on ICs

I am tempted to open, once again, the discussion about how to connect
power and ground pins to ICs on a multi-layer PCB, and how best to
bypass them.

I have held the firm belief that IC power and ground pins should
always be tied right to their planes as soon as possible, with the
shortest trace lengths. Then bypass capacitors can be added near
those pins.

Some have suggested the alternative of bringing power and ground from
the planes, first to the bypass capacitor, and then to the IC pins,
something like this:

+----------+
###| |###
| |
###| |###
vias | |
X=====###========###| |###
| | | |
X=====###========###| |###
bypass | |
capacitor ###| |###
+----------+
I.C.

I feel this is dangerous because of the added inductance. The
power/ground planes are your best high frequency bypass capacitor
(although a small one), so I'd think you want to get your IC pins
brought to them as quickly as possible, without wasting etch going to
a discrete capacitor which may not be very effective anyway if it's
above self resonance. Also the power and ground pin inductance is
effectively in series with all output drivers when they switch. So
I avoid this technique.

But I recently had a short discussion with an engineer who promoted
the latter, and insisted it was better in mixed-signal environments.
Most of my work has been straight digital lately, though I do find
myself surrounded by a smattering of mixed-signal components for such
things as ethernet.

The presumed justification is that these mixed-signal devices benefit
from the additional small filtering provided by the trace inductance.

By the way, the IC under discussion had all digital inputs and
outputs, but some internal clock re-timing, and no vendor
recommendations regarding power filtering.

Does it make sense to do this? Do I want to adopt a strategy of using
the first method for straight digital devices, and the second method
for mixed-signal devices that don't use filtered power?

Is it wise to do this with both power and ground leads? Or should
ground pins always route directly to the ground plane, with longer
traces in only the power leads? (Assuming no PECL, of course.)

Thanks for advice.
Regards,
Andy Ingraham

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