I can send tou a list of references on the subject, if you feel a
>I have a Clock chip design that has some Clock outputs on
>its VSS pin(s) and the rest of the outputs on a different VSS pin(s).
>On Silicon, we have observed that there exists interaction between
>these sets of outputs. The VDD of the outputs are separate too.
>The two sets of VSS pins are not connected on chip (except through
>the psubstrate). I would like to know how to model this substrate
>connection between the two VSS.
O O O D Xavier Aragones
O O O E Departament d'Enginyeria Electronica
O O O E Universitat Politecnica de Catalunya (UPC)
U P C Modul C4, Campus Nord, c/ Gran Capita, s/n
08034 BARCELONA (Spain)
phone. + 34 93 401 7482 e-mail: email@example.com
fax. + 34 93 401 6756 http://petrus.upc.es
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