Re: [SI-LIST] : Substrate modeling

Xavier Aragones (aragones@eel.upc.es)
Thu, 19 Nov 1998 15:14:29 +0100 (MET)

If your substrate is a epi-layer on top of a highly conductive
bulk, you may try simple models like the ones proposed by Su (IEEE J.
Solid-State Circuits, April 1993), or van Genderen (IEEE European
Design and Test conference, 1996, available on
http://dutentb.et.tudelft.nl/research/space.html). You will also find
a free tool in that web page.
If you have a uniform lightly-doped wafer, you'll probably need a more
dense resistive mesh. There is a commercial software at
http://www.snaketech.com

I can send tou a list of references on the subject, if you feel a
particular interest.

Regards,

Xavier

>Hi,
>
>I have a Clock chip design that has some Clock outputs on
>its VSS pin(s) and the rest of the outputs on a different VSS pin(s).
>
>On Silicon, we have observed that there exists interaction between
>these sets of outputs. The VDD of the outputs are separate too.
>The two sets of VSS pins are not connected on chip (except through
>the psubstrate). I would like to know how to model this substrate
>connection between the two VSS.
>
>Thanks
>Krishnan
>

____________________________________________________________________________

O O O D Xavier Aragones
O O O E Departament d'Enginyeria Electronica
O O O E Universitat Politecnica de Catalunya (UPC)
U P C Modul C4, Campus Nord, c/ Gran Capita, s/n
08034 BARCELONA (Spain)

phone. + 34 93 401 7482 e-mail: aragones@eel.upc.es
fax. + 34 93 401 6756 http://petrus.upc.es
____________________________________________________________________________

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****