For sometime I have been striving to enhance my knowledge of
parastic parameters associated with IC pins (and packages) and PCB vias
(and pads). An in-depth understanding of these parameters can be
beneficial for several reasons including:
I. Accurate creation and verification of behavioral models, which
possess parasitic parameters such as R_Package, L_package, C_Package,
R_Pin, L_Pin and C_Pin.
II. Preventing artifacts in simulation and avoiding
misinterpretation of simulaion results (waveforms). This is due to the
fact that a pin (or package) parasitic inductance which is larger than
the actual physical value can lead to an excessive hump (peak) in the
simulation waveform. A parasitic capacitance which exceeds the true
value can result in a false valley (dip) in the waveform. Such
inaccuracies or artifacts, lacking correlation with respect to the real
physical system, resemble signal integrity degradation (ringing) and can
lead to misinterpretation..
To gain insight regarding parasitic parameters let us consider two
numerical examples:
Example 1. Parasitic values for a via.
Capacitance: 0.53pF
Inductnce: 1.2 nH
(Above value for via inductance has been adapted from page 259 of
"High-Speed Design A Handbook of Black Magic" by H.W. Johnson and M.
Graham, though many believe that the nominal via inductance has a lower
value of about 0.25nH).
Example 2. Package parasitic parameters for a uBGA package:
R_Package: 0.045 Ohm
L_Package: 3.5 nH
C_Package: 0.15pF
(Note: Above values represent typical or nominal values, but an IBIS
model usually includes parasitic parameters for typical, minimum and
maximum corners. Furthermore, these parameters assume higher values for
larger IC packages such as super BGA, as expected)
In regard to this subject there are several questions of special
importance which arise, such as:
1. What is the mathematical relationship between pin parasitics
(i.e. R_Pin, C_Pin, and L_Pin) and package parasitics (i.e. R_Package,
C_Package, and L_Package) ?
2. What is the realistic range of values for package (and pin)
parasitic parameters for various types of Insertion Mounted Components
(IMCs) and Surface Mounted Components (SMCs), such as DIP, SOIC, LCC,
PLCC and various types of BGA?
3. What is the optimum technique for determination of package (and
pin) parasitics ?
4. What are the equivalent circuits for parasitic parameters?
Comprehensive answers to these types of questions can contribute to
bring about improvements in the following areas:
I. Accurate creation of IBIS models and modeling of connectors,
vias and pads.
II. Behavioral model verification and correction.
III. Simulation and waveform interpretation.
I will appreciate your thoughts and comments regarding means of
determination, modeling and quantification of parasitic parameters.
Best Regards,
Abe Riazi
SI Engineer
Anigma, Inc.
email: ariazi@anigma.com
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