Re: [SI-LIST] : Conducted EMC Testing of PLL jitter

yuan (yuan@hsmpka)
Mon, 5 Oct 1998 09:19:41 -0700 (PDT)

Hi Ray,

It will be almost impossible to inject 200mv into a very low
impedance power plane.

I think the only wany is to lift PLLvdd pin and PLLVss pins
and inject noise intothem.

-Leo
> Subject: [SI-LIST] : Conducted EMC Testing of PLL jitter
> To: yuan@boxofrain
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> FYI.
>
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> Date: Tue, 29 Sep 1998 09:51:16 -0700 (PDT)
> From: Ray Anderson <raymonda@radium.eng.sun.com>
> Subject: [SI-LIST] : Conducted EMC Testing of PLL jitter
> To: si-list@silab.eng.sun.com
> MIME-Version: 1.0
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>
> Perhaps some of the EMI/EMC savvy people on the list have
> some comments and/or opinions on how best to couple an interfering
> RF signal into the power planes of a digital board to accomplish
> some EMC testing.
>
>
> Basically I have a system (CPU's, memory, PLL's etc.) that
> runs at a clock rate of several hundred MHz. I need to do
> some tests to evaluate what effect noise on the power planes
> over the range of ~DC to 1GHz has on the PLL jitter.
>
>
> I would like to inject a signal (in the range of ~DC to 1 GHz)
> into the power planes (up to maybe 200 mv p-p amplitude) to
> see how the PLL handles the noise on it's power feed.
>
>
> I have a broadband (10KHz to 1GHz) amplifier that can provide
> an excitation level of up to 20 watts into 50 ohms.
>
>
> We believe the system power distribution system (planes, bypass
> caps etc.) looks like a broadband 50 milliohm (or less) impedance.
>
>
> The question is: would impedance matching the 50 ohm amplifier
> impedance to the sub-ohm plane impedance by means of a broadband
> ferrite transmission line transformer be a prudent thing to do,
> or is there another accepted way of doing this?
>
>
> Any comments or suggestions on alternate ways of evaluating the
> jitter performance of a system PLL in response to power supply
> noise over a wide bandwidth would be of interest.
>
> Ray Anderson
>
> Sun Microsystems Inc.
> raymonda@radium.eng.sun.com
>
>
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