[SI-LIST] : SSO - How simultaneous is simultaneous?

David Haedge (haedge@icds5.dseg.ti.com)
Wed, 7 Jan 1998 17:12:38 -0600

The question seems to be: How simultaneous is simultaneous? We recently had
this question come up on an ASIC design that had a number of 8-bit wide data
ports that could be switched simultanously. The ASIC designers simulated the
condition and applied an external clock and enabled each port. We then set the
time that the first output switched to t=0 and computed the delay for the other
signals. What we found was that about 40% switched within 0.5ns after t0, 25%
switched between 0.5ns and 1.0ns, and the remaining 35% between 1.0ns and 3.0ns.
These delays were caused by the cumulative effect of all of the internal gate
delays and interconnect between the clock and each output stage. This
'smearing' effect will cause the SSO associated noise to be somewhat lower than
the 'worst case', i.e., all signals switch at t=0. Each design will be
different, but the ASIC designers should be able to provide the 'smearing' info
and it can then be SPICE'D to give you a more realistic number for SSO noise.
In my experience, computing the worst case number can give you some pretty scary
results.

David Haedge
d-haedge@ti.com