[SI-LIST] : delay lines

Ray Anderson (raymonda@radium.eng.sun.com)
Wed, 24 Sep 1997 10:01:24 -0700 (PDT)

The following message was forwarded from Vicky at Intel.
It was indvertently sent to our admin address. When I forwarded it
to the list with her address attached, due to the wonders of
e-mail, it somehow got alinas address attached to it.

-Ray
Sun Microsystems

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Date: Wed, 24 Sep 97 16:59:00 PDT
From: Vicky Kai Lin Chiew <Vicky_Kai_Lin_Chiew@ccm.ipn.intel.com>
To: owner-si-list@silab.eng.sun.com
Subject: delay lines

Does anyone know what is the best way to design a delay line. By delay
line, I mean that the required transmission line is much longer than the
physical space of the PCB.

Most of the books showed that such a line is routed in zig-zag manner at
90 degrees cornerings. Does this 90 degree cornering have any adverse
effect to the signal integrity of such a line??

Should the 90 degree cornering be chamfered or fillet??

IS there any article published corcerning this ?

Vicky Chiew
Intel Technology Sdn Bhd.

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