Earlier, Murali Raj writes:
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This is absolutely outrageous.
I strongly object to this.
Please do not make spoil the sanctity
of a group to which people sign on for
information and knowledge exchange.
Not for receiving, as you very mildly put it,
Its people like you who give the web a bad name.
I hope you desist from such activities in the future
and start using ethical means of finding people
to work in your organization.
On Thu, 12 Feb 1998 Steve_Mango@stratus.com wrote:
-->Sorry for the "junk" mail... but if any of you signal fidelity engineers
-->are available... please read on:
-->My name is Steve Mango and I am the hiring manager of the Analog and
-->Signal Fidelity Group at Stratus (a fault tolerant computer design
-->company) in Marlboro, Ma. I have openings for signal fidelity engineers
-->to join my fast-growing team. I would prefer full time permanent
-->engineers, but I am willing to consider contractors.
-->My group must solve many high-speed technical challenges as we push
-->clock and bus speeds >100MHz. I am looking for experienced signal
Press any key to return to index.my group. [Note: These positions are for
-->USERS of signal fidelity tools to solve complex problems, rather than
-->for software developers of new software analysis tools.]
-->* Help define/diagnose/solve complex signal fidelity problems (clock
-->generation/distribution, interconnect design, timing, termination,
-->decoupling, power/ground distribution, package/connector selection,
-->* You should have at least 3-5 years experience in the signal fidelity
-->and high speed digital design field.
-->* You should have hands-on experience with modeling and simulating with
-->Quad Design tools (MOTIVE, XTK, TLC), SPICE (PSPICE and HSPICE),
-->electromagnetic field solvers (e.g., Greenfield, Pacific Numerix,
-->Maxwell 3D, etc). Candidate should be familiar with high speed board
-->interconnect routers (Allegro and CCT router preferred). Experience with
-->IBIS modeling and Interconnectix software is a major plus. Candidate
-->should also be familiar with high speed test plan development, test
-->measurements techniques and lab equipment (HP and Tektronix). Experience
-->with current high speed processors and multiple logic families is
-->desirable. Other pluses are experience with custom ASIC cell design,
-->phase lock loops, hot plug, FET switches, PCI Bus, SCSI bus, and
-->M-7 Education: BS degree minimum.
-->ItM-^Rs an exciting time here at Stratus
-->Come Join our team.
-->Please call me at (508) 490-6231
-->Or email me at: Steve_Mango@stratus.com