Having been both an EMI engineer for many years as well as a designer of
high performance interconnects, I have to make a comment about jittery clocks.
This is an invention of the EMI community and the bane of most high
performance designers when trying to meet timing requirements. Controlling
emissions from clock lines should be done by proper board and signal
integrity design, not spread spectrum techniques. The amount of problems
introduced in a 100 MHz system by introducing enough jitter to make a
difference in the spectral content of the clock spectrum is overwhelming.
If you are designing a garden variety bus (VME, FutureBus, etc.) you should
be able to control the emissions with good PWB design.
At 12:38 PM 10/29/97 +5:30, you wrote:
>A WEB source suggests that:-
>In order to reduce EMI, there should be some logic that introduces a
>jitter into the clock network. This results a pulse energy to spread
>horizontally in the frequency domain which inturn results in the
>quasi-peek energy reduced. This will cause the resultant average
>frequency reduced slightly.
>Could anybody please explain what does this mean? Will it help? If
>so, where do I get more deatiled information about this?
>Thanks for your attention,
>Shuttle Technology Ltd.,
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