RE: [SI-LIST] : How to identify SSO
Andrew Ingraham ([email protected])
Wed, 7 Jan 98 05:18:43 EST
> Upon further reflection of Praveen's question on SSO, and all of the
> responses, it seems like we are talking about two different things. Both
> of which drive the VSS/VDD pin count.
>
> One is overlap - which is defined as the time that both FETs in a
> totem-pole output stage are turned on. As you all know, this has a
> profound effect on a chip's dynamic current demand.
>
> The other one is SSO (simultaneous switching outputs) - which I would
> describe as the number of outputs - outputs that go off chip - that
> simultaneously go high (or low) and draw (or source) extra current to
> charge (or discharge) the load capacitance they see. Of course, this
> can seriously impact the amount of ground bounce and power supply droop
> a chip will see.
>
> So, do they add? Not necessarily, if the design is a synchronous one and
> the overlap is small. But if, as some of the e-mail states, the overlap
> gets up to 10 ns, then there would be a cumulative effect.
Not everyone is using "overlap" the same way. I think some used
"overlap" to mean "multiple outputs that switch nearly simultaneously,
such that their di/dt's overlap one another."
I can't imagine that the overlap current of a single buffer (according
to your first definition above) would approach 10 ns in any modern
CMOS design.
Regards,
Andy