I have either layed out or reviewed layouts for a number of boards
with gigabit dif'l pairs. The following comments are more practical
than theoretical, but I believe they are worth considering:
* Most disturbances on Gbit dif'l lines are from discontinuities
(component capacitance, package inductance, vias (especially
large ones), connectors, etc.) rather than the choice of line
The complexity of connecting to surface-mounted components
(transmitter, blocking capacitors, connectors, terminator
discretes, receiver) using vias to connect to different internal
layers, then lining up two lines one over the other while trying
to maintain matched impedance throughout weighs strongly against
the "broadside" approach.
To a lesser extent, this complexity also weighs against any
stripline approach in favor of microstrip cross sections.
While microstrip is less desirable from an EMI perspective,
dif'l pairs have much reduced emissions compared with single
ended signals. Also, the broad-band spectrum of transmitted
data helps here, too. (To be honest, though, typical IDLE
patterns are rich in Fc/2 components.)
* Most board vendors have single-ended impedance control down to
a science. However, very few seem to understand dif'l impedance.
For this reason, choosing an edge-to-edge cross section with a
spacing such that Z(difl) ~ 2*Z(single-ended) will minimize
the possibility of error.
As this conflicts with the objective of tight coupling for low
radiation and rejection of dif'l mode noise, the design guidelines
of one company who has developed such products recommends an
edge-to-edge spacing of roughly 2.5 times the trace width as
a compromise approach.
Hope that helps.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Mike Jenkins Phone: 408.433.7901 _____ LSI Logic Corp, ms/G750 Fax: 408.433.2840 LSI|LOGIC| (R) 1525 McCarthy Blvd. mailto:firstname.lastname@example.org | | Milpitas, CA 95035 http://www.lsilogic.com |_____| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~