Re: [SI-LIST] : 回覆 : [SI-LIST] : stackup impedance.

Ron Bader ([email protected])
Wed, 17 Sep 1997 10:40:07 -0700

Just an additional comment to what Weber wrote:

If the routing on adjacent signal layers in the S-S-G-P-S-S is
constrained to run perpendicular to each other and one is careful about
via placement, crosstalk should not be a problem, and the adjacent
signal layers should both behave like buried microstrips with a
(different dielectric constant for the solder mask over the outer
layer).

With respect to using the P plane as an impedance reference, John needs
to insure there are good AC low impedance return paths distributed
liberally via a matrix of appropriate capacitors between P-G for the P
plane to provide a good impedance reference.
Weber Chuang wrote:
> =

> Hi,
> =

> For S-S-G-P-S-S stackup, to avoid crosstalk, the distance
> between first signal layer and second must be much larger than the
> distance between second signal layer and power or ground plane(a=
t
> least 3 times), which in turn will result in large differences of th=
e
> trace's characteristic impedance between first signal layer and secon=
d
> , not good for signal. Is there any special reason to arrange the
> stackup in such manners? However, for the signal layer that is close=

> to the plane, formula for embeded microstrip might still work, for the=

> top or bottom layer, it will vary according to the neighboring trace in=

> the second and third signal layer accordingly. We have tried such
> stackup, lots of troubles.
> =

> regards
> weber
> =

> > -----=AD=EC=A9l=B6l=A5=F3-----
> > =B1H=A5=F3=AA=CC: John Lin - TAO [SMTP:[email protected]]
> > =B6=C7=B0e=AE=C9=B6=A1: 1997=A6~9=A4=EB17=A4=E9 =A4U=A4=C8 02:45
> > =A6=AC=A5=F3=AA=CC: 'SI_LIST'
> > =A5D=A6=AE: [SI-LIST] : stackup impedance.
> >
> > Hi,
> > Does anybody have idea about how to calculate the impedance of
> > stackup with following structures.
> >
> > S-S-G-P-S-S ( 6 layers).
> >
> > and
> >
> > G-S-S-S-S-P (6 layers).
> >
> > I checked books and tried to find equations to calculate impedance.
> > However, I cannot find any.
> >
> >
> > Best Regards,
> >
> > JOHNLIN
> > CAE Engineer of EDA Department
> > Digital Equipment Corp. Taiwan Branch
> > Email: [email protected]
> > TEL: 1-886-3-3900000 ext. 2565
> >
> >
> .-

-- =

-----------------------------------------------
Ron Bader <[email protected]>
Bader Engineering phone: 408.338.9514
28387 Big Basin Way fax: 408.338.4689
Boulder Creek, CA 95006-9007
-----------------------------------------------