Re: [SI-LIST] : Buried Capacitors

Paul Franzon (paulf@eos.ncsu.edu)
Wed, 30 Jul 1997 10:00:57 -0400

A 2 mil FR4 layer pair would give about 500 pF/in^2 which is too
small for most decoupling purposes.

However, its low inductance would make it a
good aid in filtering out high frequency noise (200MHz+ compts)
and thus help reduce EMI.

Regards,

Paul

On Jul 29, 17:49, <rharris@etdesg.trw.com> wrote:
> Subject: [SI-LIST] : Buried Capacitors
> I am trying to gain a better understanding on the concept of the buried
> capacitors, made of two (2) internal planes on a printed circuit board.
>
> We do not have a general agreement within the design community on the
use
> of this technique, so I just wanted to bounce it off of this reflector.
>
> Multi-layer PCB's have power and ground planes as a norm. This technique
> stacks some of these planes very close together (2 mil thin dielectrics)
> to act as a giant capacitor.
>
> The design uses thru-hole vias only.
>
> Are we:
> 1) reducing noise
> 2) using this as an alternative to filter-caps
> 3) using this in conjunction with filter-caps.
> 4) At what frequencies is this practice appropriate.
> 5) anything else you can add.
>
> Thanks
>
> Bob Harrison
> TRW
>-- End of excerpt from <rharris@etdesg.trw.com>

-- 

----- Paul Franzon, Associate Professor, North Carolina State University smail: ECE, Box 7911, NCSU, Raleigh NC 27695-7911 Fedex: ECE, Daniels 232, NCSU, Raleigh, NC 27695 919 515 7351, fax. 919 515 5523, http://www.ece.ncsu.edu/erl/faculty/paulf.html