Re: [SI-LIST] : Clock skew

Weston Beal (beal@lisbon.eng.hou.compaq.com)
Mon, 9 Nov 98 10:13 CST

Shimon,

What about the different loading effects of the different loads? I've
seen skews up to 1ns with matched length clock traces that did not
account for different loading effects. You probably need to simulate
and adjust lengths or at least calculate and adjust lengths.

Regards,
Weston Beal

> To: si-list <si-list@silab.Eng.Sun.COM>
> Date: Sun, 8 Nov 1998 11:59:05 +0200
> Subject: [SI-LIST] : Clock skew
>
> to avoiding clock skew between the clocks in my board, I connect eqaul
> traces to all branches, to do so I tunning the trace with square (45
> degres) loops
> like that : _____/---\__/----\__/----\_______load.
>
> 1. do you think have any problem with this configuration ?
> 2. what is a resonanble skew between clocks ?
>
> Best Regards
> Shimon turgeman
>
>
>

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