RE: [SI-LIST] : SSO noise: Through current vs. Discharge current

Peterson, James F (jfpeterson@space.honeywell.com)
Thu, 25 Sep 1997 13:13:33 -0400

John,
one of the things we talked about during the SSN banter was that the
o-buffs might only contributed a fraction of the noise generated by a
chip's SSN. other coconspirators were internal logic and undershoot at
the inputs of the chip (which caused current flow through the clamp
diodes). have you found out anything more about this in your searchings?
or maybe comment on the effectiveness/accuracy in just looking at
switching o-buffs.
thanks,
Jim

> ----------
> From: John V
> Fitzpatrick[SMTP:John.Fitzpatrick@ln.cit.alcatel.fr]
> Sent: Thursday, September 25, 1997 8:55 AM
> To: Signal Integrity Mailing List
> Cc: nirmal@ansoft.com
> Subject: [SI-LIST] : SSO noise: Through current vs. Discharge
> current
>
> Hello,
>
> Several weeks ago I asked a question to the list concerning
> simultaneous switching noise (SSN). I received many useful
> answers. Most pointed me towards Senthinathan and Prince,
> which I have ordered, but not yet received.
>
> One issue that concerned me was the influence of load
> capacitance on the SSN. The answer, it seems, depends on
> the design of the output buffer:
>
> 1) If the P and N transistors are momentarily ON,
> then the "through" current dominates, which means that
> the maximum noise amplitude is independent of the load.
> This is because the di/dt of the through current is greater
> than the di/dt of any (dis-)charge current.
>
> 2) If the output buffer is designed so that the P and N
> buffers are never both ON, then the SSN source
> is predominately the (dis)charge current. SSN increases
> with Cload up to a certain value of Cload, then plateaus
> off (Vmax).
> If the Cload is replaced by a transmission line, then
> then a simple rule is that the SSN is (Iz/Isc)*Vmax,
> where Isc is the short-circuit output current and Iz is the
> output current for a resistance equal to the impedance of
> the line.
>
> This interpretation prompts the following question:
>
> Are real-life buffers designed such that the P and N
> transistors are never ON simultaneously?
>
> Comments?
>
> Salutations,
> John
>
> --
> John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr>
> Alcatel Telecom, 4 rue de Broglie, 22304 Lannion, France
> Tel: +33(0)2.96.04.79.33 Fax: +33(0)2.96.04.85.09
>